Abstract: A method for fabricating dielectric barrier layers in integrated circuit structures such as damascene structures is provided. In one embodiment, a low-k dielectric layer formed on a substrate is provided. The low-k dielectric layer has at least one opening exposing an underlying metal layer. A first silicon carbide barrier layer is formed to conformally cover the exposed surfaces of the opening. A portion of the first silicon carbide barrier layer above the low-k dielectric layer and over the bottom of the opening is converted with an oxidation treatment into a layer of silicon oxide. The silicon oxide layer is removed above the low-k dielectric layer and from the bottom of the opening. The opening is filled with a conductive layer in electrical contact with the underlying metal layer. The conductive layer is removed above the low-k dielectric layer to a predetermined depth below the low-k dielectric layer to define a recess therebelow.

Abstract: Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Abstract: In the forming of copper interconnects for an integrated circuit, a method for dissociating copper oxides from copper surfaces is provided. An antireflective coating layer is formed over an insulating layer formed over a semiconductor substrate. An interconnect pattern is patterned and etched into said insulating layer. A diffusion barrier layer is then conformally deposited in a deposition chamber along the etched interconnect pattern, wherein the antireflective coating is removed in said chamber before deposition of the barrier layer. Copper interconnects are formed in the interconnect pattern etched in the insulating layer. A supercritical fluid is then provided on the insulating layer. The supercritical fluid is then treated to dissociate the copper oxides from the copper surfaces.

Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Abstract: In the forming of copper interconnects for an integrated circuit, a method for dissociating copper oxides from copper surfaces is provided. An antireflective coating layer is formed over an insulating layer formed over a semiconductor substrate. An interconnect pattern is patterned and etched into said insulating layer. A diffusion barrier layer is then conformally deposited in a deposition chamber along the etched interconnect pattern, wherein the antireflective coating is removed in said chamber before deposition of the barrier layer. Copper interconnects are formed in the interconnect pattern etched in the insulating layer. A supercritical fluid is then provided on the insulating layer. The supercritical fluid is then treated to dissociate the copper oxides from the copper surfaces.

Abstract: A method of forming a low-k dielectric material layer comprising the following steps. A first dielectric material sub-layer is formed over a substrate. The first dielectric material sub-layer is treated with an energy treatment to form a hardened layer on the upper surface of the first dielectric material sub-layer. A second dielectric material sub-layer is formed over the hardened layer, wherein the first dielectric sub-layer, the hardened layer and the second dielectric sub-layer comprise the low-k dielectric material layer. And a dual damascene structure and a dielectric material structure formed thereby.

Abstract: A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3? variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.

Abstract: A method for determining a material layer thickness transmissive to infrared (IR) energy in a semiconductor wafer manufacturing process including providing at least one semiconductor wafer comprising an IR transmissive layer; passing IR energy through the IR transmissive layer to produce at least one Fourier transform infrared (FTIR) spectrum; and, determining an amount of the IR transmissive layer present according to an amount of IR energy absorbed by a predetermined contributing characteristic vibrational mode portion of the FTIR spectrum.

Abstract: A method of forming a low-k dielectric material layer comprising the following steps. A first dielectric material sub-layer is formed over a substrate. The first dielectric material sub-layer is treated with an energy treatment to form a hardened layer on the upper surface of the first dielectric material sub-layer. A second dielectric material sub-layer is formed over the hardened layer, wherein the first dielectric sub-layer, the hardened layer and the second dielectric sub-layer comprise the low-k dielectric material layer. And a dual damascene structure and a dielectric material structure formed thereby.

Abstract: A method and system for monitoring the quality of a slurry utilized in a chemical mechanical polishing operation. A slurry is generally delivered through a tubular path during a chemical mechanical polishing operation. A laser light is generally transmitted from a laser light source, such that the laser light comes into contact with the slurry during the chemical mechanical polishing operation. The laser light can then be detected, after the laser light comes into contact with the slurry to thereby monitor the quality of the slurry utilized during the chemical mechanical polishing operation. The laser light that comes into contact with the slurry can be also be utilized to monitor a mixing ratio associated with the slurry.

Abstract: A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.

Abstract: A method for fabricating dielectric barrier layers in integrated circuit structures such as damascene structures is provided. In one embodiment, a low-k dielectric layer formed on a substrate is provided. The low-k dielectric layer has at least one opening exposing an underlying metal layer. A first silicon carbide barrier layer is formed to conformally cover the exposed surfaces of the opening. A portion of the first silicon carbide barrier layer above the low-k dielectric layer and over the bottom of the opening is converted with an oxidation treatment into a layer of silicon oxide. The silicon oxide layer is removed above the low-k dielectric layer and from the bottom of the opening. The opening is filled with a conductive layer in electrical contact with the underlying metal layer. The conductive layer is removed above the low-k dielectric layer to a predetermined depth below the low-k dielectric layer to define a recess therebelow.

Abstract: Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Abstract: A method and system for monitoring the quality of a slurry utilized in a chemical mechanical polishing operation. A slurry is generally delivered through a tubular path during a chemical mechanical polishing operation. A laser light is generally transmitted from a laser light source, such that the laser light comes into contact with the slurry during the chemical mechanical polishing operation. The laser light can then be detected, after the laser light comes into contact with the slurry to thereby monitor the quality of the slurry utilized during the chemical mechanical polishing operation. The laser light that comes into contact with the slurry can be also be utilized to monitor a mixing ratio associated with the slurry.

Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Abstract: A method of removing resinous organic material over a semiconductor process surface including providing a semiconductor wafer having a process surface comprising a resinous organic material; and, exposing the process surface to a supercritical CO2 containing medium further comprising at least a first solvent for a predetermined period to produce a substantially resinous organic material free and undamaged process surface.

Abstract: A method for determining a material layer thickness transmissive to infrared (IR) energy in a semiconductor wafer manufacturing process including providing at least one semiconductor wafer comprising an IR transmissive layer; passing IR energy through the IR transmissive layer to produce at least one Fourier transform infrared (FTIR) spectrum; and, determining an amount of the IR transmissive layer present according to an amount of IR energy absorbed by a predetermined contributing characteristic vibrational mode portion of the FTIR spectrum.

Abstract: In a method of forming an integrated circuit, a sacrificial layer is formed over a substrate. The sacrificial layer has a gate trench formed therein and a first layer of a first material formed over the substrate in the gate trench. A second layer of a second material is formed over the first layer in the gate trench. The first and second layers are processed to form a layer of a high-K dielectric material.

Abstract: A method and system for monitoring the quality of a slurry utilized in a chemical mechanical polishing operation. A slurry is generally delivered through a tubular path during a chemical mechanical polishing operation. A laser light is generally transmitted from a laser light source, such that the laser light comes into contact with the slurry during the chemical mechanical polishing operation. The laser light can then be detected, after the laser light comes into contact with the slurry to thereby monitor the quality of the slurry utilized during the chemical mechanical polishing operation. The laser light that comes into contact with the slurry can be also be utilized to monitor a mixing ratio associated with the slurry.