Patents by Inventor Aiguo Yan
Aiguo Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7949925Abstract: A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.Type: GrantFiled: October 11, 2006Date of Patent: May 24, 2011Assignee: MediaTek Inc.Inventors: Lidwine Martinot, Aiguo Yan, Marko Kocic, Thomas J. Barber, Jr., John Zijun Shen
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Patent number: 7924948Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.Type: GrantFiled: October 11, 2006Date of Patent: April 12, 2011Assignee: MediaTek Inc.Inventors: Marko Kocic, Aiguo Yan, Lidwine Martinot, Thomas J. Barber, Jr., John Zijun Shen
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Patent number: 7916841Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.Type: GrantFiled: October 11, 2006Date of Patent: March 29, 2011Assignee: MediaTek Inc.Inventors: Aiguo Yan, Lidwine Martinot, Marko Kocic, Paul D. Krivacek, Thomas J. Barber, Jr., John Zijun Shen
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Digital filter system whose stopband roots lie on unit circle of complex plane and associated method
Patent number: 7693923Abstract: A method is disclosed for providing a digital filter system for providing a low pass filter function to a digital input. The method includes the steps of determining a finite impulse response of the input, determining a transfer function of the finite impulse response and providing a polynomial, identifying a plurality of stopband roots of the polymonial that lie in a complex plane, identifying real and complex conjugate pairs for the plurality of stopband roots, and providing coefficients for a complex polynomial that realizes the real and complex conjugate pairs such that a plurality of adjusted stopband roots lie on a unit circle of said complex plane.Type: GrantFiled: October 27, 2005Date of Patent: April 6, 2010Assignee: Mediatek Inc.Inventors: Ayman Shabra, Aiguo Yan -
Patent number: 7649968Abstract: A timing system is disclosed for use in a wireless communication system that includes wireless transceiver and a digital baseband processing system. The timing system includes a primary clock generation system that provides a low frequency clock that is used as the reference clock for a digital signal processing system, which generates low frequency timing signals, and a secondary clock generation system that provides a high frequency clock that is used by the wireless transceiver to produce high resolution timing signals to control the timing of the wireless transceiver. The high resolution timing signals are commenced responsive to a low resolution timing signal.Type: GrantFiled: November 10, 2005Date of Patent: January 19, 2010Assignee: Mediatek Inc.Inventors: Thomas Barber, Aiguo Yan, Palle Birk, Pier Bove
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Publication number: 20090304121Abstract: A wireless receiver uses a joint detection Viterbi (JDV) algorithm to demodulate a signal that has a desired signal component and an interference signal component. The desired signal component includes a training sequence and at least one data field. The training sequence and a corresponding portion of the interference signal component is demodulated using the JDV algorithm to evaluate possible transmitted training sequences and interference signal sequences, and channel estimations for the desired signal component and the interference signal component are generated. The at least one data field is demodulated according to the JDV algorithm using the channel estimations as initial channel estimates for the JDV algorithm.Type: ApplicationFiled: August 26, 2008Publication date: December 10, 2009Inventors: Carsten Aagaard Pedersen, Navid Fatemi-Ghomi, Aiguo Yan, Jason Taylor
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Publication number: 20090304122Abstract: A receiver adaptively selects between a joint detection Viterbi demodulator and a second Viterbi demodulator to demodulate a received signal based on at least one characteristic of the received signal. The joint detection Viterbi demodulator jointly demodulates a desired signal component and an interference signal component of the received signal, and the second Viterbi demodulator demodulates the desired signal component without demodulating the interference signal component.Type: ApplicationFiled: August 26, 2008Publication date: December 10, 2009Inventors: Navid Fatemi-Ghomi, Carsten Aagaard Pedersen, Jason Taylor, Aiguo Yan
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Publication number: 20090175205Abstract: An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.Type: ApplicationFiled: August 27, 2008Publication date: July 9, 2009Inventors: Deepak Mathew, Eric Aardoom, Timothy Perrin Fisher-Jeffes, David Stephen Ivory, Carsten Aagaard Pedersen, Aiguo Yan
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Publication number: 20090165019Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.Type: ApplicationFiled: October 20, 2008Publication date: June 25, 2009Applicant: MediaTek Inc.Inventors: John Zijun Shen, Carsten Aagaard Pedersen, Deepak Mathew, Paul Donald Krivacek, Aiguo Yan, Timothy Perrin Fisher-Jeffes
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Publication number: 20090161745Abstract: A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.Type: ApplicationFiled: August 11, 2008Publication date: June 25, 2009Inventors: Carsten Aagaard Pedersen, John Zijun Shen, Aiguo Yan, Deepak Mathew, Marko Kocic, Timothy Perrin Fisher-Jeffes, Thomas Keller
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Publication number: 20090081973Abstract: Methods and apparatus are provided for controlling transmitted power in a wireless system. The method includes generating information to be transmitted as a series of signal bursts, with a time interval between successive signal bursts, controlling individually a power level of each of said signal bursts with a power control signal to provide output signal bursts to be transmitted, and asserting a new power value of the power control signal during the time interval preceding each signal burst. The wireless system can be a TDSCDMA wireless system, and the signal bursts can be uplink signal bursts.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Applicant: Analog Devices, Inc.Inventors: Aiguo Yan, Jonathan Richard Strange, Bernard Mark Tenbroek, Deepak Mathew, Liang Ma
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Patent number: 7379752Abstract: One embodiment of the invention is directed to operating, in a wireless network, a device that is designed for operation in a different wireless network. In one embodiment, a device designed to operate in a GSM wireless network may be used to communicate in a PHS wireless network.Type: GrantFiled: October 13, 2004Date of Patent: May 27, 2008Assignee: MediaTek Inc.Inventor: Aiguo Yan
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Publication number: 20080089448Abstract: A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.Type: ApplicationFiled: October 11, 2006Publication date: April 17, 2008Applicant: Analog Devices, Inc.Inventors: Lidwine Martinot, Aiguo Yan, Marko Kocic, Thomas J. Barber, John Zijun Shen
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Publication number: 20080080645Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.Type: ApplicationFiled: October 11, 2006Publication date: April 3, 2008Applicant: Analog Devices, Inc.Inventors: Marko Kocic, Aiguo Yan, Lidwine Martinot, Thomas J. Barber, John Zijun Shen
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Publication number: 20080080468Abstract: A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.Type: ApplicationFiled: June 12, 2007Publication date: April 3, 2008Applicant: Analog Devices, Inc.Inventors: John Zijun Shen, Paul D. Krivacek, Thomas J. Barber, Lidwine Martinot, Aiguo Yan, Marko Kocic
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Publication number: 20080081575Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.Type: ApplicationFiled: September 28, 2006Publication date: April 3, 2008Applicant: Analog Devices, Inc.Inventors: Deepak Mathew, Aiguo Yan, Krishnan Vishwanathan, Eric Aardoom, Timothy Fisher-Jeffes
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Publication number: 20080080542Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.Type: ApplicationFiled: September 28, 2006Publication date: April 3, 2008Applicant: Analog Devices, Inc.Inventors: Krishnan Vishwanathan, Deepak Mathew, Eric Aardoom, Lidwine Martinot, Aiguo Yan, Timothy Fisher-Jeffes, Paul D. Krivacek
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Publication number: 20080080444Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.Type: ApplicationFiled: September 28, 2006Publication date: April 3, 2008Applicant: Analog Devices, Inc.Inventors: Timothy Fisher-Jeffes, Deepak Mathew, Krishnan Vishwanathan, Eric Aardoom, Aiguo Yan
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Publication number: 20080080638Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.Type: ApplicationFiled: October 11, 2006Publication date: April 3, 2008Applicant: Analog Devices, Inc.Inventors: Aiguo Yan, Lidwine Martinot, Marko Kocic, Paul D. Krivacek, Thomas J. Barber, John Zijun Shen
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Publication number: 20080080443Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.Type: ApplicationFiled: September 28, 2006Publication date: April 3, 2008Applicant: Analog Devices, Inc.Inventors: Lidwine Martinot, Deepak Mathew, Krishnan Vishwanathan, Eric Aardoom, Aiguo Yan, Timothy Fisher-Jeffes