Patents by Inventor Ajit Paranjpe
Ajit Paranjpe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250109493Abstract: A chemical vapor deposition system includes a reaction chamber and a removable wafer carrier including a wafer carrier body that is configured to support a wafer. The system includes a removable cover plate that supports the wafer carrier body and a susceptor base is disposed below the cover plate that supports the cover plate. The removable cover plate is in a nested arrangement with respect to the susceptor base as a result of first nesting structure of the removable cover plate mating with a second nesting structure of the susceptor base.Type: ApplicationFiled: September 27, 2024Publication date: April 3, 2025Applicant: VEECO INSTRUMENTS INC.Inventors: Johannes Kaeppeler, Ajit Paranjpe
-
Publication number: 20240425973Abstract: A method of cleaning wafer carriers includes the steps of: 1) loading a wafer carrier in need of cleaning into a cleaning chamber, injecting one or more cleaning gases into the cleaning chamber; 2) activating the one or more cleaning gases at a temperature ranging from about 400° C. to about 1000° C. under a pressure ranging from about 100 Torr to about 760 Torr; 3) exposing surfaces of the wafer carrier to the activated one or more cleaning gases; and 4) inspecting the wafer carrier surfaces using one or more surface characterization tools to determine if the wafer carrier has been cleaned.Type: ApplicationFiled: September 4, 2024Publication date: December 26, 2024Applicant: VEECO INSTRUMENTS INC.Inventors: Alexander I. Gurary, Mandar Deshpande, Ajit Paranjpe
-
Patent number: 12104242Abstract: A chemical vapor deposition system for semiconductor wafer production is disclosed. The system includes a process cluster coupled to a first end of a transfer chamber. The process cluster is maintained at a pressure that is lower than atmospheric pressure. The process cluster is also configured to apply epitaxial layers on one or more wafers loaded onto a wafer carrier. The system also includes an automatic factory interface coupled to a second end of the transfer chamber. The automatic factory interface is maintained at atmospheric pressure. The system includes one or more wafer carrier cleaning modules coupled to the automatic factory interface and configured to clean one or more of the wafer carriers without removing the wafer carriers from the chemical vapor deposition system.Type: GrantFiled: May 8, 2020Date of Patent: October 1, 2024Assignee: VEECO INSTRUMENTS INC.Inventors: Alexander I. Gurary, Mandar Deshpande, Ajit Paranjpe
-
Publication number: 20240175132Abstract: A multi-wafer metal organic chemical vapor deposition system in which adjacent wafers positioned within the system rotate about their own axes, including a reaction chamber comprising an exhaust system including a peripheral port, a multi-wafer carrier comprising a wafer carrier body and a plurality of wafer carrier discs supported within the wafer carrier body, wherein adjacent wafer carrier discs of the plurality wafer carrier discs are configured and the wafer carrier body are configured to rotate at different speeds, a multi-zone injection block positioned over the wafer carrier body, a central gas port positioned in the center of the wafer carrier body functions as a gas exhaust, and a multi-zone heater assembly positioned beneath the multi-wafer carrier.Type: ApplicationFiled: November 27, 2023Publication date: May 30, 2024Applicant: VEECO INSTRUMENTS INC.Inventors: Ajit Paranjpe, Alexander Gurary, Bojan Mitrovic
-
Publication number: 20240175133Abstract: A multi-wafer metal organic chemical vapor deposition system in which adjacent wafers positioned within the system rotate about their own axes, including a reaction chamber comprising an exhaust system including a peripheral port, a multi-wafer carrier comprising a wafer carrier body and a plurality of wafer carrier discs supported within the wafer carrier body, wherein adjacent wafer carrier discs of the plurality wafer carrier discs are configured and the wafer carrier body are configured to rotate at different speeds, a multi-zone injection block positioned over the wafer carrier body, a central gas port positioned in the center of the wafer carrier body that can be configured as a gas exhaust or a gas injection port, and a multi-zone heater assembly positioned beneath the multi-wafer carrier.Type: ApplicationFiled: November 27, 2023Publication date: May 30, 2024Applicant: VEECO INSTRUMENTS INC.Inventors: Ajit Paranjpe, Johannes Kaeppeler, Alexander Gurary
-
Publication number: 20200354828Abstract: A chemical vapor deposition system for semiconductor wafer production is disclosed. The system includes a process cluster coupled to a first end of a transfer chamber. The process cluster is maintained at a pressure that is lower than atmospheric pressure. The process cluster is also configured to apply epitaxial layers on one or more wafers loaded onto a wafer carrier. The system also includes an automatic factory interface coupled to a second end of the transfer chamber. The automatic factory interface is maintained at atmospheric pressure. The system includes one or more wafer carrier cleaning modules coupled to the automatic factory interface and configured to clean one or more of the wafer carriers without removing the wafer carriers from the chemical vapor deposition system.Type: ApplicationFiled: May 8, 2020Publication date: November 12, 2020Inventors: Alexander I. Gurary, Mandar Deshpande, Ajit Paranjpe
-
Patent number: 10167554Abstract: Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.Type: GrantFiled: December 21, 2011Date of Patent: January 1, 2019Assignee: Veeco Instruments Inc.Inventors: Bojan Mitrovic, Guanghua Wei, Eric A. Armour, Ajit Paranjpe
-
Publication number: 20180230596Abstract: Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.Type: ApplicationFiled: April 6, 2018Publication date: August 16, 2018Applicant: Veeco Instruments Inc.Inventors: Bojan Mitrovic, Guanghua Wei, Eric A. Armour, Ajit Paranjpe
-
Patent number: 9978934Abstract: This disclosure provides various methods for improved etching of spin-transfer torque random access memory (STT-RAM) structures. In one example, the method includes (1) ion beam etch of the stack just past the MTJ at near normal incidence, (2) a short clean-up etch at a larger angle in a windowed mode to remove any redeposited material along the sidewall that extends from just below the MTJ to just above the MTJ, (3) deposition of an encapsulant with controlled step coverage to revert to a vertical or slightly re-entrant profile from the tapered profile generated by the etch steps, (4) ion beam etch of the remainder of the stack at near normal incidence while preserving the encapsulation along the sidewall of the MTJ, (5) clean-up etch at a larger angle and windowed mode to remove redeposited materials from the sidewalls, and (6) encapsulation of the etched stack.Type: GrantFiled: October 30, 2015Date of Patent: May 22, 2018Assignee: VEECO Instruments Inc.Inventors: Ajit Paranjpe, Boris Druz, Katrina Rook, Narasimhan Srinivasan
-
Patent number: 9938621Abstract: Methods are provided for treating wafers using a wafer carrier rotated about an axis. The wafer carrier is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.Type: GrantFiled: May 11, 2016Date of Patent: April 10, 2018Assignee: Veeco Instruments Inc.Inventors: Bojan Mitrovic, Guanghua Wei, Eric A. Armour, Ajit Paranjpe
-
Patent number: 9761671Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.Type: GrantFiled: December 30, 2014Date of Patent: September 12, 2017Assignee: Veeco Instruments, Inc.Inventors: Ajit Paranjpe, Craig Metzner, Joe Lamb
-
Publication number: 20170125668Abstract: This disclosure provides various methods for improved etching of spin-transfer torque random access memory (STT-RAM) structures. In one example, the method includes (1) ion beam etch of the stack just past the MTJ at near normal incidence, (2) a short clean-up etch at a larger angle in a windowed mode to remove any redeposited material along the sidewall that extends from just below the MTJ to just above the MTJ, (3) deposition of an encapsulant with controlled step coverage to revert to a vertical or slightly re-entrant profile from the tapered profile generated by the etch steps, (4) ion beam etch of the remainder of the stack at near normal incidence while preserving the encapsulation along the sidewall of the MTJ, (5) clean-up etch at a larger angle and windowed mode to remove redeposited materials from the sidewalls, and (6) encapsulation of the etched stack.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Inventors: Ajit Paranjpe, Boris Druz, Katrina Rook, Narasimhan Srinivasan
-
Publication number: 20170076972Abstract: A wafer carrier for a plurality of wafers, the wafer carrier having a platen with a plurality of openings and a plurality of wafer retention platforms, the platen configured to rotate about a first axis, the plurality of wafer retention platforms configured to rotate about respective second axes, each of the wafer retention platforms rotatably coupled to one of the plurality of openings by friction reducing bearings, the platen and the plurality of wafer retention platforms and the friction reducing bearings all being constructed of the same material.Type: ApplicationFiled: September 15, 2016Publication date: March 16, 2017Inventors: Sandeep Krishnan, Lukas Urban, Alexander Gurary, Keng Moy, Ajit Paranjpe
-
Publication number: 20160251758Abstract: Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.Type: ApplicationFiled: May 11, 2016Publication date: September 1, 2016Inventors: Bojan Mitrovic, Guanghua Wei, Eric A. Armour, Ajit Paranjpe
-
Publication number: 20160160387Abstract: A linear cluster deposition system includes a plurality of reaction chambers positioned in a linear horizontal arrangement. First and second reactant gas manifolds are coupled to respective process gas input port of each of the reaction chambers. An exhaust gas manifold having a plurality of exhaust gas inputs is coupled to the exhaust gas output port of each of the plurality of reaction chambers. A substrate transport vehicle transports at least one of a substrate and a substrate carrier that supports at least one substrate into and out of substrate transfer ports of each of the reaction chambers. At least one of a flow rate of process gas into the process gas input port of each of the reaction chambers and a pressure in each of the reaction chambers being chosen so that process conditions are substantially the same in at least two of the reaction chambers.Type: ApplicationFiled: January 15, 2016Publication date: June 9, 2016Applicant: Veeco Instruments IncInventors: William E. Quinn, Alexander Gurary, Ajit Paranjpe, Maria D. Ferreira, Roger P. Fremgen, Eric A. Armour
-
Patent number: 9356188Abstract: A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.Type: GrantFiled: September 8, 2014Date of Patent: May 31, 2016Assignee: Veeco Instruments, Inc.Inventors: Ajit Paranjpe, Jia Lee, Craig Metzner
-
Publication number: 20160118291Abstract: Wafer carriers and methods for moving wafers in a reactor. The wafer carrier may include a platen with a plurality of compartments and a plurality of wafer platforms. The platen is configured to rotate about a first axis. Each of the wafer platforms is associated with one of the compartments and is configured to rotate about a respective second axis relative to the respective compartment. The platen and the wafer platforms rotate with different angular velocities to create planetary motion therebetween. The method may include rotating a platen about a first axis of rotation. The method further includes rotating each of a plurality of wafer platforms carried on the platen and carrying the wafers about a respective second axis of rotation and with a different angular velocity than the platen to create planetary motion therebetween.Type: ApplicationFiled: January 4, 2016Publication date: April 28, 2016Inventors: Adrian Celaru, Todd Arthur Luse, Ajit Paranjpe, Joseph Scandariato, Qingfu Tang
-
Publication number: 20150187888Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.Type: ApplicationFiled: December 30, 2014Publication date: July 2, 2015Inventors: Ajit Paranjpe, Craig Metzner, Joe Lamb
-
Publication number: 20150069420Abstract: A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.Type: ApplicationFiled: September 8, 2014Publication date: March 12, 2015Inventors: Ajit Paranjpe, Jia Lee, Craig Metzner
-
Publication number: 20140326186Abstract: A VPE reactor is improved by providing temperature control to within 0.5° C., and greater process gas uniformity via novel reactor shaping, unique wafer motion structures, improvements in thermal control systems, improvements in gas flow structures, improved methods for application of gas and temperature, and improved control systems for detecting and reducing process variation.Type: ApplicationFiled: July 16, 2014Publication date: November 6, 2014Inventors: Ajit Paranjpe, Alexander Gurary, William Quinn