Abstract: A system and method for integrating flash management and deduplication with marker based reference set handling may include a dynamic reference set that is elastic and can include non-contiguous reference blocks. The method may further include determining the first reference block of the plurality of reference blocks for continued encoding, the first reference block having an identifier, and associating the identifier of the first reference block with a second reference set. Some implementations of the method may further include receiving a first plurality of data blocks in an incoming data stream, the first plurality of data blocks including a first data block, and encoding the first data block using the first reference block associated with the second reference set.

Abstract: Technologies are disclosed for providing developers with rule output indicating that issues are or may be present in the code they are developing. Such rule output can include or be accompanied by guidelines and/or best practices structured to aid developers in becoming aware of and resolving the issues. In one example, this involves identifying the issues, making available a mechanism of further investigating the issues, and providing best practices and/or recommended solutions for the issues. Finally, the technologies disclosed may automate application of the recommended solutions. The notifications and accompanying guidance/automation and the like can be provided at design-time, compile-time, and/or run-time with the notifications and accompanying guidance/automation integrated into editors, compilers, debuggers, and other development environment tools providing true real-time and in situ development experience.

Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

Abstract: A method and system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization are described. The method includes providing boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the boundary conditions including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros, performing macro-level physical synthesis at each of the plurality of macros, and providing feedback to the unit level controller based on the macro-level physical synthesis performed at each of the plurality of macros, the feedback including a proposed new location for the movable pins of each of the plurality of blocks. The method also includes performing hierarchical co-optimization at the unit level controller based on the feedback from each of the plurality of macros to determine locations for the movable pins.

Abstract: Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.

Abstract: A performance state machine is controlled in part by identifying notifications from an execution trace of an application program, through rapid automatic comparison of trace events to notification events for notification categories. Some notification categories include application startup, page outline load, page data load start, page data load finish, page to page transition, application input, window size change, media query, binding update, page background task start, page background task finish, developer-defined scenario start, and developer-defined scenario finish. Notifications may reflect heuristics such as the time from startup to first frame submission. A state is placed in the performance state machine for each identified notification, with aggregate application performance data for each transition between identified notifications.

Abstract: A method and system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization are described. The method includes providing boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the boundary conditions including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros, performing macro-level physical synthesis at each of the plurality of macros, and providing feedback to the unit level controller based on the macro-level physical synthesis performed at each of the plurality of macros, the feedback including a proposed new location for the movable pins of each of the plurality of blocks. The method also includes performing hierarchical co-optimization at the unit level controller based on the feedback from each of the plurality of macros to determine locations for the movable pins.

Abstract: Mobile devices may obtain applications from an application market infrastructure. The applications may consume data from a data allocation that has been purchased from a mobile data provider. A user may assign a sub-allocation of the data allocation with a specific application, for use by the application. When the sub-allocation is depleted, the application may alert the user and also give the user an opportunity to purchase additional data. If the user accepts an offer to purchase additional data, the application calls the application market infrastructure to process a purchase transaction for the additional data. The application market infrastructure interacts with the user to complete the transaction and then instructs the mobile data provider to allocation additional data to the mobile device of the user, which is then added to the sub-allocation associated with the application.

Abstract: A sequence of contiguous pages in an erase block in a non-volatile memory device is programmed and erased. Next, all of the pages in the erase block are programmed with data. Then, the data is read back and verified to determine whether there is an error in the data. When there is an error in the data, then the last page in the sequence is identified as being unstable. If there is no error in the data, then the last page in that sequence is identified as being stable. Thus, the recorded information identifies a point of instability in the erase block. Instabilities can be stabilized by performing additional writes to fill the partially filled word line.

Abstract: Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.

Abstract: Diagnosing equipment coupled to a generator. A condition of the equipment is diagnosed based on information provided by signals from a generator operationally connected to the equipment or other signals associated with an engine. Different types of degradation are distinguished based on discerning characteristics within the information. Thus, a degraded equipment component can be identified in a manner that reduces service induced delay.

Abstract: Mobile devices may obtain applications from an application market infrastructure. The applications may consume data from a data allocation that has been purchased from a mobile data provider. A user may assign a sub-allocation of the data allocation with a specific application, for use by the application. When the sub-allocation is depleted, the application may alert the user and also give the user an opportunity to purchase additional data. If the user accepts an offer to purchase additional data, the application calls the application market infrastructure to process a purchase transaction for the additional data. The application market infrastructure interacts with the user to complete the transaction and then instructs the mobile data provider to allocation additional data to the mobile device of the user, which is then added to the sub-allocation associated with the application.

Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

Abstract: A memory apparatus and methods are provided for preventing read errors on weak pages in a non-volatile memory system. In one example, a method includes identifying a weak page in a non-volatile memory device along a word line, wherein the weak page is partially written with at least some data; buffering data associated with the weak page to a weak page buffer that is coupled in communication with the non-volatile memory device; determining that an amount of data in the weak page buffer has reached a predetermined data level; and writing the data from the weak page buffer into the weak page along the word line in the non-volatile memory device.

Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

Abstract: A method and system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization are described. The method includes providing boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the boundary conditions including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros, performing macro-level physical synthesis at each of the plurality of macros, and providing feedback to the unit level controller based on the macro-level physical synthesis performed at each of the plurality of macros, the feedback including a proposed new location for the movable pins of each of the plurality of blocks. The method also includes performing hierarchical co-optimization at the unit level controller based on the feedback from each of the plurality of macros to determine locations for the movable pins.

Abstract: A method and system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization are described. The method includes providing boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the boundary conditions including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros, performing macro-level physical synthesis at each of the plurality of macros, and providing feedback to the unit level controller based on the macro-level physical synthesis performed at each of the plurality of macros, the feedback including a proposed new location for the movable pins of each of the plurality of blocks. The method also includes performing hierarchical co-optimization at the unit level controller based on the feedback from each of the plurality of macros to determine locations for the movable pins.

Abstract: Mobile devices may obtain applications from an application market infrastructure. The applications may consume data from a data allocation that has been purchased from a mobile data provider. A user may assign a sub-allocation of the data allocation with a specific application, for use by the application. When the sub-allocation is depleted, the application may alert the user and also give the user an opportunity to purchase additional data. If the user accepts an offer to purchase additional data, the application calls the application market infrastructure to process a purchase transaction for the additional data. The application market infrastructure interacts with the user to complete the transaction and then instructs the mobile data provider to allocation additional data to the mobile device of the user, which is then added to the sub-allocation associated with the application.

Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

Abstract: A storage device may include a non-volatile memory; and a controller. The controller may be configured to store a plurality of blocks of data in the memory, determine exclusive-or (XOR) parity data for the plurality of blocks, and store the XOR parity data in the memory; store a second block of data in the memory. The controller may be further configured to generate updated XOR parity data by at least XORing a first block of the plurality of blocks and the second block of data with the XOR parity data to remove the first block from the XOR parity data and to add the second block to the XOR parity data, and store the updated XOR parity data in the memory.