Patents by Inventor Akash Bansal
Akash Bansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10938605Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.Type: GrantFiled: January 23, 2020Date of Patent: March 2, 2021Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Brian S. Leibowitz, Jade M. Kizer, Thomas H. Greer, Akash Bansal
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Publication number: 20210050043Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.Type: ApplicationFiled: August 6, 2020Publication date: February 18, 2021Applicant: Rambus Inc.Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
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Patent number: 10878878Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: March 20, 2020Date of Patent: December 29, 2020Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Publication number: 20200349991Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.Type: ApplicationFiled: April 20, 2020Publication date: November 5, 2020Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
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Publication number: 20200312422Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: ApplicationFiled: March 19, 2020Publication date: October 1, 2020Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
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Publication number: 20200294577Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: ApplicationFiled: March 20, 2020Publication date: September 17, 2020Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Patent number: 10770124Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.Type: GrantFiled: December 17, 2018Date of Patent: September 8, 2020Assignee: Rambus Inc.Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
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Publication number: 20200228376Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.Type: ApplicationFiled: January 23, 2020Publication date: July 16, 2020Inventors: Hae-Chang Lee, Brian S. Leibowitz, Jade M. Kizer, Thomas H. Greer, Akash Bansal
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Patent number: 10672450Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: September 24, 2018Date of Patent: June 2, 2020Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Patent number: 10650872Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.Type: GrantFiled: December 10, 2018Date of Patent: May 12, 2020Assignee: Rambus Inc.Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
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Patent number: 10622053Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: February 14, 2019Date of Patent: April 14, 2020Assignee: Rambus inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Patent number: 10614869Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: December 28, 2018Date of Patent: April 7, 2020Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Patent number: 10600497Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: GrantFiled: December 19, 2017Date of Patent: March 24, 2020Assignee: Rambus Inc.Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
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Patent number: 10560291Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.Type: GrantFiled: November 7, 2018Date of Patent: February 11, 2020Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Brian S. Leibowitz, Jade M. Kizer, Thomas H. Greer, Akash Bansal
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Patent number: 10431290Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: September 24, 2018Date of Patent: October 1, 2019Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Publication number: 20190213679Abstract: According to a first aspect, there is provided a cross-border payment server comprising: at least one processor; at least one memory including computer program code; the at least one memory and the computer program code configured to, with the at least one processor, cause the cross-border payment server at least to: that receive, from an account, an indication of a fund amount to finance cross-border transactions; calculate assets purchased by the fund amount; supply the account with the purchased assets; update the assets held in the account resulting from assets traded during each cross-border transaction involving the account; and effect a return of funds in response to sale of the assets held in the account.Type: ApplicationFiled: December 31, 2018Publication date: July 11, 2019Applicant: MASTERCARD INTERNATIONAL INCORPORATEDInventors: Bharathi R., Ashutosh Sharan, Akash Bansal, Navneet Kumar
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Publication number: 20190206458Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.Type: ApplicationFiled: December 17, 2018Publication date: July 4, 2019Applicant: Rambus Inc.Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
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Publication number: 20190180805Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.Type: ApplicationFiled: December 10, 2018Publication date: June 13, 2019Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
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Publication number: 20190180813Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: ApplicationFiled: February 14, 2019Publication date: June 13, 2019Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
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Publication number: 20190173696Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.Type: ApplicationFiled: November 7, 2018Publication date: June 6, 2019Inventors: Hae-Chang Lee, Brian S. Leibowitz, Jade M. Kizer, Thomas H. Greer, Akash Bansal