Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., ½, ¼ or ? of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

Abstract: Techniques for performing timing calibration for an integrated circuit (IC) device are described. During operation, a first integrated circuit device transmits a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference. The first integrated circuit device additionally transmits a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference. Next, the first integrated circuit generates a timing offset for transmitting data from the first integrated circuit device. This timing offset is derived from information received from a second integrated circuit device sampling the first calibration pattern and the second calibration pattern.

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Abstract: An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured in a loopback mode to transmit and receive the test data sequence. The second transceiver receives the test data sequence received by the first transceiver and is configured in a loopback mode to transmit and receive the test data sequence. The test sequence analyzer determines whether the test data sequence received by the second transceiver matches the test data sequence generated by the test sequence generator.

Abstract: A low overhead coding technique is disclosed. In one particular exemplary embodiment, the low overhead coding technique may be realized as a method for coding information comprising receiving a block of information, and encoding the block of information such that a first value of a first symbol in the encoded block of information is not equal to a second value of an adjacent second symbol in the encoded block of information or a third value of an adjacent last symbol in a previously encoded block of information.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data stripe over an associated data channel. The plurality of data channels are organized into at least one group and each group has an associated parity channel to transmit a parity stripe generated based on the data stripes within the group. The apparatus also includes a reception module to receive the plurality of data stripes and the at least one parity stripe. The apparatus further includes a controller to control the operation of the apparatus.

Abstract: An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured in a loopback mode to transmit and receive the test data sequence. The second transceiver receives the test data sequence received by the first transceiver and is configured in a loopback mode to transmit and receive the test data sequence. The test sequence analyzer determines whether the test data sequence received by the second transceiver matches the test data sequence generated by the test sequence generator.

Abstract: The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path.

Abstract: A low overhead coding technique is disclosed. In one particular exemplary embodiment, the low overhead coding technique may be realized as a method for coding information comprising receiving a block of information, and encoding the block of information such that a first value of a first symbol in the encoded block of information is not equal to a second value of an adjacent second symbol in the encoded block of information or a third value of an adjacent last symbol in a previously encoded block of information.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data stripe over an associated data channel. The plurality of data channels are organized into at least one group and each group has an associated parity channel to transmit a parity stripe generated based on the data stripes within the group. The apparatus also includes a reception module to receive the plurality of data stripes and the at least one parity stripe. The apparatus further includes a controller to control the operation of the apparatus.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data strip over an associated serial channel, a reception module to receive the plurality of data stripes over the associated serial channels and track a number of errors per channel, and a controller to deactivate a serial channel and reconfigure said transmission module and said reception module to utilize remaining data channels for striping data if the number of errors in the serial channel exceeds a threshold.

Abstract: The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path.

Abstract: The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path.