Patents by Inventor Akhilesh Kumar

Akhilesh Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070130353
    Abstract: A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
    Type: Application
    Filed: January 6, 2006
    Publication date: June 7, 2007
    Inventors: Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra Mannava, Rajee Ram, Sujoy Sen, Srinand Venkatesan, Kiran Padwekar
  • Publication number: 20070118678
    Abstract: A method is described that involves directing a configuration request through a switch core to a configuration agent. The method also involves processing the configuration request at the configuration agent. The method also involves sending a configuration command derived from the configuration request from the configuration agent to the switch core. The method also involves executing the configuration command at an agent to which the configuration command pertains.
    Type: Application
    Filed: November 21, 2005
    Publication date: May 24, 2007
    Inventors: Eric Delano, Ioannis Schoinas, Akhilesh Kumar, Doddaballapur Jayasimha
  • Patent number: 7167957
    Abstract: A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: January 23, 2007
    Assignee: Intel Corporation
    Inventors: Manoj Khare, Lily P. Looi, Akhilesh Kumar
  • Patent number: 7124252
    Abstract: An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output bus directed to the distributed, coherent memory. An input/output coherent cache buffer receives the prefetched data and is kept coherent with the distributed, coherent memory and with other caching agents in the system.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: Manoj Khare, Akhilesh Kumar, Lily P. Looi, Kenneth C. Creta
  • Publication number: 20060184480
    Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.
    Type: Application
    Filed: December 13, 2004
    Publication date: August 17, 2006
    Inventors: Mani Ayyar, Eric Delano, Ioannis Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose Vargas
  • Publication number: 20060126656
    Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
    Type: Application
    Filed: December 13, 2004
    Publication date: June 15, 2006
    Inventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddaballapur Jayasimha, Murugasamy Nachimuthu, Phanindra Mannava
  • Publication number: 20060106993
    Abstract: A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.
    Type: Application
    Filed: December 28, 2005
    Publication date: May 18, 2006
    Inventors: Manoj Khare, Lily Looi, Akhilesh Kumar
  • Patent number: 7016304
    Abstract: A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: March 21, 2006
    Assignee: Intel Corporation
    Inventors: Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra K. Mannava, Rajee S. Ram, Sujoy Sen, Srinand Venkatesan, Kiran Padwekar
  • Patent number: 6976129
    Abstract: A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a request for a current copy of a data line. The method further includes finding the data line within a cache-coherent multi-node system. The method also includes copying the data line without disturbing a state associated with the data line. The method also includes providing a copy of the data line in response to the request. The method also includes determining if the data line is a last data line of a transaction based on a known transaction length of the transaction.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Kenneth C. Creta, Manoj Khare, Lily P. Looi, Akhilesh Kumar
  • Patent number: 6971098
    Abstract: Embodiments of the present invention relate to methods and apparatus for managing transaction requests in a multi-node architecture. In one embodiment, a previously received ordered group request may be forwarded to a destination agent. Whether a next received ordered group request belongs to a same ordered group as the previously received ordered group request may be determined. Additionally, it may be determined whether an ordering fork is encountered if the next received ordered group request belongs to the same ordered group as the previously received ordered group request. If an ordering fork is encountered, it may be determined whether a request complete message for the previously received ordered group request has been received.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: November 29, 2005
    Assignee: Intel Corporation
    Inventors: Manoj Khare, Akhilesh Kumar, Ioannis Schoinas, Lily Pao Looi
  • Publication number: 20050218041
    Abstract: An apparatus and process for separating a feed liquefied natural gas containing at least methane and a hydrocarbon less volatile the methane, into a product natural gas enriched with methane and lean in hydrocarbon less volatile than methane and a heavier fraction lean in methane and enriched with hydrocarbon less volatile than methane. The process includes heating the feed liquefied natural gas in a heat exchanger, passing the heated fluid into a distillation column, withdrawing the heavier fraction from a bottom of the column, and withdrawing a residue gas from a top of the column. The process also includes liquefying at least part of the residue gas in the heat exchanger, refluxing a part of the liquid portion of the fluid obtained in the liquefying step into the column, and withdrawing, as the product narutal gas, the remainder of the liquid portion.
    Type: Application
    Filed: September 17, 2004
    Publication date: October 6, 2005
    Applicant: TOYO ENGINEERING CORPORATION
    Inventors: Nobuhiro Yoshida, Shoichi Yamaguchi, Susumu Ohara, Akhilesh Kumar
  • Publication number: 20050204193
    Abstract: In some embodiments an apparatus includes a transmission error detector to detect an error of a transmission of an interconnect and a transmitting agent to retry the transmission in response to the detected error. The apparatus also includes a hard failure detector to detect a hard failure of the interconnect if the retry is unsuccessful, and a transmission width reducer to reduce a transmission width of the interconnect in response to the hard failure detector. Other embodiments are described and claimed.
    Type: Application
    Filed: March 12, 2004
    Publication date: September 15, 2005
    Inventors: Phanindra Mannava, Victor Lee, Akhilesh Kumar, Doddaballapur Jayasimha, Ioannis Schoinas
  • Publication number: 20050144488
    Abstract: The current method and apparatus provides a novel approach to manage the power consumption of a high speed I/O interface by selectively turning off non-essential portions of the interface. Here only part of the interface is powered off as compared to the whole interface being turned off. From the upper layers (protocol/system) perspective, the interface is always “on”. Thus, this mechanism reduces link power by selectively turning off portions of the link, yet allowing for fast wake up in an interface power management architecture.
    Type: Application
    Filed: March 25, 2004
    Publication date: June 30, 2005
    Inventors: Victor Lee, Phanindra Mannava, Akhilesh Kumar, Sanjay Dabral
  • Patent number: 6866772
    Abstract: An improved furfural extraction process for lube oil base-stock production from hydrocarbon oils containing aromatic type material by the addition of a solvent comprising of furfural and a co-solvent, said process being conducted in a continuous countercurrent extraction column that facilitates phase separation and increases the raffinate yield while maintaining the same raffinate quality measured by raffinate refractive index.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: March 15, 2005
    Assignee: Indian Oil Corporation Limited
    Inventors: Raman Naduhatty Selai, Devotta Irudayaraj, Bhaskar Mani, Venketesan Phoobalan, Rewat Bijendra Singh, Rawat Bachan Singh, Bhatnagar Akhilesh Kumar
  • Patent number: 6859864
    Abstract: A method and apparatus are described for providing an implicit write-back in a distributed shared memory environment implementing a snoop based architecture. A requesting node submits a single read request to a snoop based architecture controller switch. The switch recognizes that another node other than the requesting node and the home node for the desired data has a copy of the data. The switch directs the request to the responding node that is not the home node. The responding node, having modified the data, provides a single response back to the switch that causes the switch to both update the data at the home node and answer the requesting node. The updating of the data at the home node is done without receiving an explicit write instruction from the requesting node.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: February 22, 2005
    Assignee: Intel Corporation
    Inventors: Manoj Khare, Lily P. Looi, Akhilesh Kumar, Kenneth C. Creta
  • Publication number: 20050022100
    Abstract: Systems and methods of retraining a receiver provide for determining a minimum transition density for a derived clock data link to the receiver. A retraining flit is generated based on the minimum transition density. In one approach, the retraining flit is generated by defining control data and payload data for the retraining flit. Error detection data is determined for the retraining flit based on the control and the payload data. The control data, the payload data and the error detection data have sufficient transitions to meet the minimum transition density.
    Type: Application
    Filed: July 22, 2003
    Publication date: January 27, 2005
    Inventors: Victor Lee, Phanindra Mannava, Akhilesh Kumar, Sanjay Dabral
  • Patent number: 6842830
    Abstract: A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.
    Type: Grant
    Filed: March 31, 2001
    Date of Patent: January 11, 2005
    Assignee: Intel Corporation
    Inventors: Manoj Khare, Lily P. Looi, Akhilesh Kumar
  • Publication number: 20040268061
    Abstract: A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.
    Type: Application
    Filed: July 20, 2004
    Publication date: December 30, 2004
    Inventors: Manoj Khare, Lily P. Looi, Akhilesh Kumar
  • Patent number: 6826619
    Abstract: A method of sending messages from a node to a receiving agent. In one embodiment, if a outbound message that is stored in a buffer in the node is unsuccessfully sent to the receiving agent more than a threshold number of times, outbound messages currently stored in the buffer are sent to the receiving agent. It is determined that these outbound messages have been successfully sent before any other outbound messages are sent to the receiving agent. In a further embodiment, an outbound message is successfully sent if a success confirmation message is received for the outbound message from the receiving agent. In a still further embodiment, a retry response is received from the receiving agent for an outbound message if a buffer in the receiving agent that stores incoming outbound messages does not have room for the outbound message.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: November 30, 2004
    Assignee: Intel Corporation
    Inventors: Manoj Khare, Akhilesh Kumar, Sin Sim Tan
  • Patent number: 6805790
    Abstract: A process and an apparatus for the preparation of petroleum hydrocarbon solvent with improved color stability from crude oils having high concentration of nitrogenous compounds which comprises passing said petroleum hydrocarbon stream containing substantial amount of nitrogenous compounds over a column of molecular sieves modified clays at ambient to elevated temperature and pressure maintaining the feed in the liquid state, thereby obtaining the petroleum hydrocarbon stream with desired color stability.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: October 19, 2004
    Assignee: India Oil Corporation Limited
    Inventors: Anurag Ateet Gupta, Suresh Kumar Puri, Muniaswamy Rajesh, Ambrish Kumar Misra, Bijendra Singh Rawat, Akhilesh Kumar Bhatnagar