Patents by Inventor Akhilesh Kumar

Akhilesh Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210200915
    Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. The methods can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC); performing a thermal simulation for each respective template of the IC based on a sequence of power patterns of tiles of the respective template; and training a neural network with a plurality of training data collected via thermal simulations performed for the templates of the IC. These systems and methods can use a machine learning predictor, that has been trained to determine a transient temperature rise across an entire IC, and then append the determined transient temperature rise to a system level thermal profile of the IC.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Inventors: Akhilesh Kumar, Norman Chang, Hsiming Pan, Jimin Wen, Deqi Zhu, Wenbo Xia, Wen-Tze Chuang, En-Cih Yang, Karthik Srinivasan, Ying-Shiun Li
  • Publication number: 20210173983
    Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 10, 2021
    Inventors: Norman Chang, Hsiming Pan, Jimin Wen, Deqi Zhu, Wenbo Xia, Akhilesh Kumar, Wen-Tze Chuang, En-Cih Yang, Karthik Srinivasan, Ying-Shiun Li
  • Publication number: 20210157739
    Abstract: Disclosed embodiments relate to a cache line eviction algorithm. In one example, a system includes a last level cache (LLC) having multiple ways, each allocated to one of multiple priorities, each having specified minimum and maximum ways to occupy, a cache control circuit (CCC) to store an incoming cache line (CL) having a requestor priority to an invalid CL, if any, otherwise, when the requestor priority is a lowest priority and has an occupancy of one or more, or when the occupancy is at a maximum, to evict a least recently used (LRU) CL of the requestor priority, otherwise, when the occupancy is between a minimum and a maximum, to evict a LRU CL of the requestor or a lower priority, otherwise, when the occupancy is less than the minimum, to evict a LRU CL, if any, of the lower priority, and otherwise, to evict a LRU CL of a higher priority.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Applicant: Intel Corporation
    Inventors: Neha GHOLKAR, Akhilesh KUMAR
  • Publication number: 20200395332
    Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.
    Type: Application
    Filed: June 12, 2019
    Publication date: December 17, 2020
    Inventors: Nishant LAKHERA, Akhilesh Kumar Singh, Chee Seng Foong
  • Publication number: 20200202244
    Abstract: Machine assisted systems and methods for detecting unreliable circuit patterns are described. These systems and methods can use a machine learning classifier, that has been trained to recognize such circuit patterns, to detect the unreliable circuit patterns without requiring computationally expensive simulations of a circuit netlist which can be over a million devices (e.g. over a million FETs). The classifier, once trained, can recognize unreliable circuit patterns quickly and can be updated over time as new unreliable circuit patterns are discovered from simulations or other sources.
    Type: Application
    Filed: September 24, 2019
    Publication date: June 25, 2020
    Inventors: Akhilesh Kumar, Hui Ding, Norman Chang
  • Publication number: 20200185319
    Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: Akhilesh Kumar Singh, Nishant Lakhera, Chee Seng Foong
  • Publication number: 20200138941
    Abstract: Methods and devices are provided for treating a food allergy in a subject in need thereof. The method entails delivering an effective amount of an allergen associated with the food allergy into the subject's cutis skin layer. Delivering the allergen is carried out by inserting one or more allergen-coated solid microneedles into the subject's skin. The one or more solid microneedles each has a base, shaft and tip, and when inserted in the subject, do not extend beyond the cutis. The allergen is allowed to dissociate from the one or more microneedles while inserted in the subject's cutis. Once the allergen disassociates, the one or more microneedles is removed from the subject's skin.
    Type: Application
    Filed: May 31, 2018
    Publication date: May 7, 2020
    Inventors: Harvinder Singh Gill, Akhilesh Kumar Shakya
  • Publication number: 20200013711
    Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 9, 2020
    Inventors: Akhilesh Kumar Singh, Nishant Lakhera, Chee Seng Foong
  • Publication number: 20190372911
    Abstract: Techniques and mechanisms for interconnecting network circuitry of an integrated circuit (IC) die and physical layer (PHY) circuits of the same IC die. In an embodiment, nodes of the network circuitry include first routers and processor cores, where the first routers are coupled to one another in an array configuration which includes rows and columns. First interconnects each extend to couple both to a corresponding one of the PHY circuits and to a corresponding one of the first routers. For each of one or more of the first interconnects, a respective one or more rows (or one or more columns) of the array configuration extend between the corresponding PHY and the corresponding router. In another embodiment, the network circuitry comprises network clusters which each include a different respective row of the array configuration.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Inventors: Akhilesh Kumar, Surhud Khare
  • Patent number: 10431534
    Abstract: Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: October 1, 2019
    Assignee: NXP USA, Inc.
    Inventors: Nishant Lakhera, Gilles Montoriol, Trung Duong, Akhilesh Kumar Singh, Navas Khan Oratti Kalandar
  • Publication number: 20190267616
    Abstract: The present disclosure relates generally to an electrode produced with a non-toxic solvent, resulting in a homogeneous mixture with uniform distributions of a conductive additive and a binder. Electrodes produced according to the present disclosure feature narrow binder particle size distribution, which distinguishes such electrodes from typical electrodes produced via a N-Methyl-Pyrrolidone (NMP) process. The resulting microstructure promotes the flow of current through the electrode and has an improved cycling stability due, in part, to the binder's and the conductive additive's ability to bind with the active material particles used in the fabrication of the electrode.
    Type: Application
    Filed: February 28, 2019
    Publication date: August 29, 2019
    Inventors: Rajshekar DAS GUPTA, Elmira MEMARZADEH, Sankar DAS GUPTA, Bjorn Haugseter, Tom Henriksen, Lars Ole Valøen, Akhilesh Kumar Srivastava
  • Publication number: 20190221113
    Abstract: The present disclosure relates to system(s) and method(s) for generating an alert based on change in traffic pattern. The system receives historic traffic data and current traffic data, associated with each road segment, from a set of road segments. Further, the system identifies a change traffic pattern based on analysing the historic traffic pattern and the current traffic pattern, using data analytics and a machine learning algorithm. Furthermore, the system identifies a sub-set of road segments, from the set of road segments, based on comparison of the change in traffic pattern and a pre-defined threshold. The system further determines root cause of change in traffic pattern by analysing the sub-set of road segments. Further, the system generates an alert for updating one or more road segments, from the sub-set of road segments, based on the root cause of change in traffic pattern.
    Type: Application
    Filed: January 15, 2019
    Publication date: July 18, 2019
    Inventors: Arvind Kumar MAURYA, Akhilesh Kumar GUPTA
  • Patent number: 10338915
    Abstract: A first code update is received having a first code change. It is determined whether the first code change of the first code update can be implemented on a first reference code version on which at least one code change of a second code update has been undone.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: July 2, 2019
    Assignee: SAP SE
    Inventors: Setu Saxena, Akhilesh Kumar, Christoph Vehns
  • Publication number: 20190181079
    Abstract: Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.
    Type: Application
    Filed: January 8, 2018
    Publication date: June 13, 2019
    Inventors: Nishant Lakhera, Gilles Montoriol, Trung Duong, Akhilesh Kumar Singh, Navas Khan Oratti Kalandar
  • Publication number: 20190157222
    Abstract: Embodiments are provided herein for a packaged semiconductor device that includes a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and an isolation structure on the outer surface of the RDL structure around one or more contact pads of the plurality of contact pads, wherein a height of the isolation structure is at least two thirds of a height of the external connections.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 23, 2019
    Inventors: Nishant LAKHERA, Andrew Jefferson MAWER, Akhilesh Kumar SINGH, Navas Khan ORATTI KALANDAR
  • Publication number: 20190103365
    Abstract: Embodiments for a packaged semiconductor device are provided herein, which includes a substrate; an antenna module attached to a top surface of the substrate, the antenna module including an antenna; an electronic component attached to the top surface of the substrate, the electronic component communicatively coupled to the antenna module through electrical connections in the substrate; a first portion of mold body that encapsulates the antenna module; a second portion of mold body that encapsulates the electronic component, wherein the second portion of mold body is separated from the first portion of mold body by at least a first trench; and a shielding layer that covers the second portion of mold body.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Akhilesh Kumar SINGH, Nishant Lakhera, Navas Khan Oratti Kalandar
  • Patent number: 10153482
    Abstract: The present invention relates to a method for manufacturing slurry for coating of electrodes for use in lithium ion batteries, wherein the method comprises mixing active materials with a binder into a binder solution, and adding an organic carbonate to the binder solution to generate the slurry. The present invention also relates to a method for manufacturing electrodes for a lithium battery cell, wherein the method comprises mixing active materials with a binder into a binder solution, adding an organic carbonate to the binder solution to generate slurry, wherein the above adding step is carried out at temperature above melting temperature of the organic carbonate, coating electrode material with the slurry, drying the coating on the electrode material by drying the organic carbonate, and surface treatment of the slurry so that the electrode is prepared for use in a lithium ion battery cell.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: December 11, 2018
    Assignee: ELECTROVAYA INC.
    Inventors: Bjorn Haugseter, Tom Henriksen, Lars Ole Valøen, Akhilesh Kumar Srivastava
  • Publication number: 20180142207
    Abstract: The present invention is a method of creating a population of hemogenic endothelial cells with arterial specification and enhanced T cell potential. In one embodiment, the method uses ETS transgene induction at the mesodermal stage of differentiation. In another embodiment, the method activates ERK and NOTCH signaling at the mesodermal stage of differentiation.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 24, 2018
    Inventors: Igor I. Slukvin, Mi Ae Park, Akhilesh Kumar
  • Publication number: 20180136930
    Abstract: A first code update is received having a first code change. It is determined whether the first code change of the first code update can be implemented on a first reference code version on which at least one code change of a second code update has been undone.
    Type: Application
    Filed: November 11, 2016
    Publication date: May 17, 2018
    Applicant: SAP SE
    Inventors: Setu Saxena, Akhilesh Kumar, Christoph Vehns
  • Publication number: 20180119104
    Abstract: The present invention relates generally to methods and compositions useful for therapeutic vascular tissue engineering. In particular, the present invention provides methods for generating substantially pure populations of vasculogenic cells from human mesenchymal progenitors, and methods and compositions for clinical applications in the field of regenerative medicine.
    Type: Application
    Filed: December 8, 2017
    Publication date: May 3, 2018
    Inventors: Igor Slukvin, Akhilesh Kumar