Patents by Inventor Aki Dote

Aki Dote has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220366011
    Abstract: A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process that includes executing search processing that repeatedly execute selecting, determining, and state changing according to a predetermined order for searching for a solution to a problem represented by an energy function including a plurality of state variables. The search processing includes counting a number of times it is determined that the value of the state variable of a change candidate is not to be continuously changed, and correcting, with an offset, a change amount of the energy function corresponding to the change in the value of the state variable of the change candidate when the counted number of times reaches a predetermined number. The determining includes determine, after the change amount is corrected, whether to change the value of the state variable of the change candidate based on the corrected change amount is performed.
    Type: Application
    Filed: February 3, 2022
    Publication date: November 17, 2022
    Applicant: FUJITSU LIMITED
    Inventor: Aki DOTE
  • Patent number: 11334646
    Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: hold values of a plurality of state variables included in an evaluation function representing energy, and outputs, every certain number of trials, the values of the plurality of state variables; compute, when a state transition occurs in response to changing of one of the values of the plurality of state variables, an energy change value for each state transition based on a weight value selected based on an update index value; and determine a first offset value based on a plurality of the energy change values such that at least one of the state transitions is allowed, outputs a plurality of first evaluation values obtained by adding the first offset value to the plurality of energy change values, and outputs, every certain number of trials, the first offset value.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: May 17, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Aki Dote, Hirotaka Tamura
  • Publication number: 20210319154
    Abstract: A sampling method includes: executing a state update process; executing a repetition count calculation process; executing an exchange control process; and executing an output process, the state update process being configured to hold values of a plurality of state variable groups each including a plurality of state variables, the plurality of state variables being included in an evaluation function indicating energy of an Ising model, and generate a state transition by changing any of the plurality of state variables in each attempt on the basis of a temperature value, in which different values are respectively associated with the plurality of state variable groups, and an amount of change in the energy due to a change in any of the plurality of state variables, the output process being configured to output values of the plurality of state variables and an expected value at a predetermined interval.
    Type: Application
    Filed: February 2, 2021
    Publication date: October 14, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Aki Dote, Hirotaka Tamura
  • Publication number: 20200272682
    Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: hold values of a plurality of state variables included in an evaluation function representing energy, and outputs, every certain number of trials, the values of the plurality of state variables; compute, when a state transition occurs in response to changing of one of the values of the plurality of state variables, an energy change value for each state transition based on a weight value selected based on an update index value; and determine a first offset value based on a plurality of the energy change values such that at least one of the state transitions is allowed, outputs a plurality of first evaluation values obtained by adding the first offset value to the plurality of energy change values and outputs, every certain number of trials the first offset value.
    Type: Application
    Filed: February 20, 2020
    Publication date: August 27, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Aki Dote, Hirotaka TAMURA
  • Patent number: 10388632
    Abstract: A semiconductor device includes, a plurality of semiconductor dies formed using semiconductor substrates, plane orientations of which are the same, and the plurality of the semiconductor dies are stacked such that a crystal orientation of at least one layer is different from other layers.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: August 20, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Aki Dote
  • Patent number: 10319667
    Abstract: An electronic device includes: a substrate that includes a first penetration hole; a first electrode that is located on a first surface of the substrate so as to cover the first penetration hole; and a first penetrating electrode that is located in the first penetration hole and is in contact with or away from the first electrode depending on temperature.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: June 11, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shoichi Miyahara, Aki Dote, Hideki Kitada
  • Patent number: 10283434
    Abstract: An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: May 7, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Taiji Sakai, Seiki Sakuyama, Nobuhiro Imaizumi, Aki Dote
  • Publication number: 20180366445
    Abstract: A semiconductor device includes, a plurality of semiconductor dies formed using semiconductor substrates, plane orientations of which are the same, and the plurality of the semiconductor dies are stacked such that a crystal orientation of at least one layer is different from other layers.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 20, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Aki Dote
  • Patent number: 10008436
    Abstract: A semiconductor device includes: a semiconductor substrate; a wiring layer provided on a front-surface side of the semiconductor substrate; a through-via that penetrates through the semiconductor substrate from a back-surface side of the semiconductor substrate and is coupled to a wire included in the wiring layer; and a stress relaxation part that protrudes toward a through-via side and is disposed on a section in the wire and coupled to the through-via, the stress relaxation part including at least one insulating portion containing an insulating material having a smaller thermal expansion coefficient than a material of the through-via.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: June 26, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Aki Dote, Takeshi Ishitsuka, Hideki Kitada
  • Publication number: 20180061740
    Abstract: An electronic device includes: a substrate that includes a first penetration hole; a first electrode that is located on a first surface of the substrate so as to cover the first penetration hole; and a first penetrating electrode that is located in the first penetration hole and is in contact with or away from the first electrode depending on temperature.
    Type: Application
    Filed: July 5, 2017
    Publication date: March 1, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Shoichi Miyahara, Aki Dote, Hideki Kitada
  • Publication number: 20170125359
    Abstract: An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.
    Type: Application
    Filed: October 20, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Taiji Sakai, Seiki Sakuyama, Nobuhiro Imaizumi, Aki Dote
  • Patent number: 9596767
    Abstract: An electronic component includes: a substrate; wiring provided on the substrate, and including an uneven section at an edge portion of the wiring in plain view; and an insulating film provided on the substrate and on the wiring. And a method of manufacturing an electronic component includes: forming, on a substrate, wiring including an uneven section at an edge portion of the wiring in plain view; and forming an insulating film on the substrate and on the wiring.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: March 14, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Aki Dote
  • Publication number: 20160351474
    Abstract: A semiconductor device includes: a semiconductor substrate; a wiring layer provided on a front-surface side of the semiconductor substrate; a through-via that penetrates through the semiconductor substrate from a back-surface side of the semiconductor substrate and is coupled to a wire included in the wiring layer; and a stress relaxation part that protrudes toward a through-via side and is disposed on a section in the wire and coupled to the through-via, the stress relaxation part including at least one insulating portion containing an insulating material having a smaller thermal expansion coefficient than a material of the through-via.
    Type: Application
    Filed: March 25, 2016
    Publication date: December 1, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Aki Dote, Takeshi ISHITSUKA, Hideki Kitada
  • Publication number: 20150373850
    Abstract: An electronic component includes: a substrate; wiring provided on the substrate, and including an uneven section at an edge portion of the wiring in plain view; and an insulating film provided on the substrate and on the wiring. And a method of manufacturing an electronic component includes: forming, on a substrate, wiring including an uneven section at an edge portion of the wiring in plain view; and forming an insulating film on the substrate and on the wiring.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 24, 2015
    Applicant: FUJITSU LIMITED
    Inventor: Aki Dote
  • Patent number: 8652854
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: February 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
  • Patent number: 8324671
    Abstract: A semiconductor device has a ferroelectric capacitor having a ferroelectric film, an interlayer insulating film having a first layer formed on the ferroelectric capacitor, a plug and a wiring connecting to the ferroelectric capacitor, and a dummy plug in the vicinity of the ferroelectric capacitor.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: December 4, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Aki Dote, Kazutoshi Izumi
  • Publication number: 20120171785
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Application
    Filed: March 12, 2012
    Publication date: July 5, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
  • Patent number: 8153448
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: April 10, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
  • Publication number: 20090280577
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Application
    Filed: May 12, 2009
    Publication date: November 12, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Tomohiro TAKAMATSU, Junichi WATANABE, Ko NAKAMURA, Wensheng WANG, Naoyuki SATO, Aki DOTE, Kenji NOMURA, Yoshimasa HORII, Masaki KURASAWA, Kazuaki TAKAI
  • Patent number: 7547933
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: June 16, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai