Patents by Inventor Aki Dote

Aki Dote has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090280577
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Application
    Filed: May 12, 2009
    Publication date: November 12, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Tomohiro TAKAMATSU, Junichi WATANABE, Ko NAKAMURA, Wensheng WANG, Naoyuki SATO, Aki DOTE, Kenji NOMURA, Yoshimasa HORII, Masaki KURASAWA, Kazuaki TAKAI
  • Patent number: 7547933
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: June 16, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai
  • Patent number: 7518173
    Abstract: A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed on the upper electrode and having a thickness of a half of or thinner than a thickness of the upper electrode; an interlayer insulating film burying the ferroelectric capacitor and the metal film; a conductive plug formed through the interlayer insulating film, reaching the metal film and including a conductive glue film and a tungsten body; and an aluminum wiring formed on the interlayer insulating film and connected to the conductive plug. A new problem near an upper electrode contact is solved which may otherwise be caused by adopting a W plug over the F capacitor.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: April 14, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Yukinobu Hikosaka, Mitsushi Fujiki, Kazutoshi Izumi, Naoya Sashida, Aki Dote
  • Publication number: 20080197391
    Abstract: A semiconductor device has a ferroelectric capacitor having a ferroelectric film, an interlayer insulating film having a first layer formed on the ferroelectric capacitor, a plug and a wiring connecting to the ferroelectric capacitor, and a dummy plug in the vicinity of the ferroelectric capacitor.
    Type: Application
    Filed: February 13, 2008
    Publication date: August 21, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Aki Dote, Kazutoshi Izumi
  • Publication number: 20080191252
    Abstract: A semiconductor device with a first insulating film formed on a semiconductor substrate; a capacitor formed on the first insulating film and including a lower electrode, a ferroelectric film and an upper electrode; a second insulating film formed on the capacitor and the first insulating film; a first contact hole formed in the second insulating film; and a first conductive plug formed in the first contact hole and having a multilayer structure and including a first aluminum film.
    Type: Application
    Filed: December 17, 2007
    Publication date: August 14, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Ko NAKAMURA, Aki DOTE
  • Publication number: 20070184595
    Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.
    Type: Application
    Filed: March 23, 2007
    Publication date: August 9, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Jirou Miura, Mitsushi Fujiki, Aki Dote, Tomohiro Takamatsu
  • Patent number: 7211850
    Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: May 1, 2007
    Assignee: Fujitsu Limited
    Inventors: Jirou Miura, Mitsushi Fujiki, Aki Dote, Tomohiro Takamatsu
  • Publication number: 20060175642
    Abstract: In a ferroelectric capacitor structure 30 in which a lower electrode and an upper electrode are coupled capacitively with each other through a ferroelectric film, when the upper electrode is formed into a two-layer structure in which a conductive oxide film and an oxidation-resistant metal film are stacked, a protective film is formed on the oxidation-resistant metal film, and the upper electrode of which upper surface alone is covered with the protective film is pattern formed.
    Type: Application
    Filed: May 27, 2005
    Publication date: August 10, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Aki Dote, Genichi Komuro
  • Publication number: 20060157762
    Abstract: A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed on the upper electrode and having a thickness of a half of or thinner than a thickness of the upper electrode; an interlayer insulating film burying the ferroelectric capacitor and the metal film; a conductive plug formed through the interlayer insulating film, reaching the metal film and including a conductive glue film and a tungsten body; and an aluminum wiring formed on the interlayer insulating film and connected to the conductive plug. A new problem near an upper electrode contact is solved which may otherwise be caused by adopting a W plug over the F capacitor.
    Type: Application
    Filed: May 16, 2005
    Publication date: July 20, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Yukinobu Hikosaka, Mitsushi Fujiki, Kazutoshi Izumi, Naoya Sashida, Aki Dote
  • Patent number: 7038264
    Abstract: A first interlayer insulation film is formed, on which a SiO2 cap film is then formed, and degassing of moisture in the first interlayer insulation film and the SiO2 cap film is preformed by heat treatment. Then, an Al2O3 film is formed on the SiO2 cap film. Subsequently, heat treatment is performed on the Al2O3 in an oxidation atmosphere, thereby accelerating oxidation of its surface. Thereafter, on the Al2O3 film, a platinum film, a PLZT film, and an IrO2 film are formed and patterned, thereby forming a ferroelectric capacitor including an upper electrode, a capacity insulation film, and a lower electrode.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: May 2, 2006
    Assignee: Fujitsu Limited
    Inventors: Katsuyoshi Matsuura, Hideyuki Noshiro, Aki Dote
  • Publication number: 20050161716
    Abstract: A first interlayer insulation film is formed, on which a SiO2 cap film is then formed, and degassing of moisture in the first interlayer insulation film and the SiO2 cap film is preformed by heat treatment. Then, an Al2O3 film is formed on the SiO2 cap film. Subsequently, heat treatment is performed on the Al2O3 in an oxidation atmosphere, thereby accelerating oxidation of its surface. Thereafter, on the Al2O3 film, a platinum film, a PLZT film, and an IrO2 film are formed and patterned, thereby forming a ferroelectric capacitor including an upper electrode, a capacity insulation film, and a lower electrode.
    Type: Application
    Filed: June 2, 2004
    Publication date: July 28, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Katsuyoshi Matsuura, Hideyuki Noshiro, Aki Dote
  • Publication number: 20050072998
    Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.
    Type: Application
    Filed: June 4, 2004
    Publication date: April 7, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Jirou Miura, Mitsushi Fujiki, Aki Dote, Tomohiro Takamatsu
  • Publication number: 20040113189
    Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.
    Type: Application
    Filed: October 29, 2003
    Publication date: June 17, 2004
    Inventors: Tomohiro Takamatsu, Junichi Watanabe, Ko Nakamura, Wensheng Wang, Naoyuki Sato, Aki Dote, Kenji Nomura, Yoshimasa Horii, Masaki Kurasawa, Kazuaki Takai