Patents by Inventor Akie Yutani
Akie Yutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11508777Abstract: An infrared solid state imaging device includes: a first PN junction diode has a first shortest length that is a shortest length from a first junction surface to a second junction surface; a PN junction diode has a second shortest length that is a shortest length from the second junction surface to a third junction surface, the second shortest length being different from the first shortest length; an insulating film serving as an element isolation region which establishes electrical isolation between a first region of the first PN junction diode and a fourth region of the second PN junction diode, and so on; and a metal wire provided on a second region of the first PN junction diode and a third region of the second PN junction diode, wherein the first PN junction diode and the second PN junction diode are connected in series.Type: GrantFiled: September 26, 2018Date of Patent: November 22, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Akie Yutani
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Publication number: 20200373347Abstract: An infrared solid state imaging device includes: a first PN junction diode has a first shortest length that is a shortest length from a first junction surface to a second junction surface; a PN junction diode has a second shortest length that is a shortest length from the second junction surface to a third junction surface, the second shortest length being different from the first shortest length; an insulating film serving as an element isolation region which establishes electrical isolation between a first region of the first PN junction diode and a fourth region of the second PN junction diode, and so on; and a metal wire provided on a second region of the first PN junction diode and a third region of the second PN junction diode, wherein the first PN junction diode and the second PN junction diode are connected in series.Type: ApplicationFiled: September 26, 2018Publication date: November 26, 2020Applicant: Mitsubishi Electric CorporationInventor: Akie YUTANI
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Patent number: 10439092Abstract: This infrared ray detection element has a diode part that includes serially connected first and second p-n junction diodes. The diode part has: n-type and p-type first regions in a well shape that are adjacent to each other; a p-type second region that constitutes a first p-n junction diode with the n-type first region; and an n-type second region that constitutes a second p-n junction diode with the p-type first region. The n-type and p-type first regions are respectively provided with n-type and p-type third regions that electrically connect the first p-n junction diode and the second p-n junction diode via a conductive material. The n-type first region has a p-type fourth region provided between the p-type first region and the p-type second region. The p-type first region has an n-type fourth region provided between the n-type first region and the n-type second region.Type: GrantFiled: May 23, 2017Date of Patent: October 8, 2019Assignee: Mitsubishi Electric CorporationInventor: Akie Yutani
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Publication number: 20190267508Abstract: This infrared ray detection element has a diode part that includes serially connected first and second p-n junction diodes. The diode part has: n-type and p-type first regions in a well shape that are adjacent to each other; a p-type second region that constitutes a first p-n junction diode with the n-type first region; and an n-type second region that constitutes a second p-n junction diode with the p-type first region. The n-type and p-type first regions are respectively provided with n-type and p-type third regions that electrically connect the first p-n junction diode and the second p-n junction diode via a conductive material. The n-type first region has a p-type fourth region provided between the p-type first region and the p-type second region. The p-type first region has an n-type fourth region provided between the n-type first region and the n-type second region.Type: ApplicationFiled: May 23, 2017Publication date: August 29, 2019Applicant: Mitsubishi Electric CorporationInventor: Akie YUTANI
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Patent number: 10157955Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: GrantFiled: January 19, 2017Date of Patent: December 18, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akie Yutani, Yasutaka Nishioka
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Publication number: 20170133430Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: ApplicationFiled: January 19, 2017Publication date: May 11, 2017Inventors: Akie YUTANI, Yasutaka NISHIOKA
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Patent number: 9583532Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: GrantFiled: February 8, 2016Date of Patent: February 28, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akie Yutani, Yasutaka Nishioka
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Publication number: 20160155772Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: ApplicationFiled: February 8, 2016Publication date: June 2, 2016Inventors: Akie YUTANI, Yasutaka NISHIOKA
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Patent number: 9281329Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: GrantFiled: May 15, 2015Date of Patent: March 8, 2016Assignee: RENESAS ELETRONICS CORPORATIONInventors: Akie Yutani, Yasutaka Nishioka
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Publication number: 20150249103Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: ApplicationFiled: May 15, 2015Publication date: September 3, 2015Inventors: Akie YUTANI, Yasutaka NISHIOKA
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Patent number: 9064771Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating fAh and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: GrantFiled: April 21, 2014Date of Patent: June 23, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akie Yutani, Yasutaka Nishioka
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Publication number: 20140225174Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Akie YUTANI, Yasutaka Nishioka
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Patent number: 8728853Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: GrantFiled: April 24, 2009Date of Patent: May 20, 2014Assignee: Renesas Electronics CorporationInventors: Akie Yutani, Yasutaka Nishioka
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Publication number: 20120037968Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: ApplicationFiled: April 24, 2009Publication date: February 16, 2012Inventors: Akie Yutani, Yasutaka Nishioka
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Patent number: 8058166Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.Type: GrantFiled: October 13, 2010Date of Patent: November 15, 2011Assignee: Renesas Electronics CorporationInventors: Kazuhito Ichinose, Akie Yutani
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Publication number: 20110027982Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.Type: ApplicationFiled: October 13, 2010Publication date: February 3, 2011Applicant: Renesas Electronics CorporationInventors: Kazuhito ICHINOSE, Akie YUTANI
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Patent number: 7834404Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.Type: GrantFiled: September 9, 2009Date of Patent: November 16, 2010Assignee: Renesas Electronics CorporationInventors: Kazuhito Ichinose, Akie Yutani
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Publication number: 20090321848Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.Type: ApplicationFiled: September 9, 2009Publication date: December 31, 2009Applicant: Renesas Technology Corp.Inventors: Kazuhito Ichinose, Akie Yutani
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Patent number: 7598171Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.Type: GrantFiled: January 4, 2007Date of Patent: October 6, 2009Assignee: Renesas Technology Corp.Inventors: Kazuhito Ichinose, Akie Yutani
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Publication number: 20070173050Abstract: A barrier metal film such as a TiN film is formed in a contact hole or a via hole. Then, a W nucleation film is formed on the barrier metal film by CVD that reduces WF6 gas with B2H6 gas. Subsequently, a W plug is formed as a contact plug or a via plug on the W nucleation film by CVD.Type: ApplicationFiled: January 19, 2007Publication date: July 26, 2007Inventors: Kazuhito Ichinose, Akie Yutani