Patents by Inventor Akie Yutani

Akie Yutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070161218
    Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.
    Type: Application
    Filed: January 4, 2007
    Publication date: July 12, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Kazuhito Ichinose, Akie Yutani
  • Publication number: 20060113676
    Abstract: A barrier metal layer having a two-layer structure of a titanium film and a titanium nitride film is formed on the inner surface of a through hole. The titanium film and the titanium nitride film are formed on a main surface of an interlayer insulating film as well. In forming the barrier metal layer, a deposition device is used that is capable of high-directivity sputtering using a titanium target, and includes a substrate bias system biasing a semiconductor substrate to a high frequency voltage to attract sputter particles from the titanium target to the semiconductor substrate. This allows the titanium nitride film to be formed as an amorphous metal film.
    Type: Application
    Filed: November 9, 2005
    Publication date: June 1, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Kazuhito Ichinose, Akie Yutani
  • Patent number: 6746876
    Abstract: A method for manufacturing a capacitor is provided which can form a lower electrode having a high aspect ratio without suffering deterioration of the capacitor electric characteristics even when a platinum-group metal is adopted as the material of the lower electrode and a metal oxide having a high dielectric constant is adopted as the material of the dielectric film. Holes (8) that reach contact plugs (2) are formed in an insulating film (7). Then a dielectric film (9) is formed on the surfaces of the holes (8). Next the dielectric film (9) on the bottoms of the holes (8) are etched away to form holes (18) reaching the contact plugs (2). Lower electrodes (11) are then formed to fill the holes (8) and (18).
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: June 8, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hiromi Itoh, Yoshikazu Tsunemine, Keiichiro Kashihara, Akie Yutani, Tomonori Okudaira
  • Patent number: 6686621
    Abstract: A semiconductor device which includes a capacitor wherein the capacitance of the capacitor can be prevented from being lowered even in the case that the capacitor is miniaturized. A core insulating film having the core of the capacitor formed above a semiconductor substrate, a capacitor lower electrode formed so as to cover side surfaces of this core insulating film, a capacitor dielectric film formed so as to cover the surface of this capacitor lower electrode and the upper surface of the core insulating film and a capacitor upper electrode formed so as to cover the surface of this core insulating film are provided so that the bottom surface of the core insulating film is positioned lower than the bottom surface of the capacitor lower electrode.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: February 3, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Akie Yutani
  • Publication number: 20030228733
    Abstract: A method for manufacturing a capacitor is provided which can form a lower electrode having a high aspect ratio without suffering deterioration of the capacitor electric characteristics even when a platinum-group metal is adopted as the material of the lower electrode and a metal oxide having a high dielectric constant is adopted as the material of the dielectric film. Holes (8) that reach contact plugs (2) are formed in an insulating film (7). Then a dielectric film (9) is formed on the surfaces of the holes (8). Next the dielectric film (9) on the bottoms of the holes (8) are etched away to form holes (18) reaching the contact plugs (2). Lower electrodes (11) are then formed to fill the holes (8) and (18).
    Type: Application
    Filed: December 6, 2002
    Publication date: December 11, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hiromi Itoh, Yoshikazu Tsunemine, Keiichiro Kashihara, Akie Yutani, Tomonori Okudaira
  • Publication number: 20030015675
    Abstract: A semiconductor device which includes a capacitor wherein the capacitance of the capacitor can be prevented from being lowered even in the case that the capacitor is miniaturized. A core insulating film having the core of the capacitor formed above a semiconductor substrate, a capacitor lower electrode formed so as to cover side surfaces of this core insulating film, a capacitor dielectric film formed so as to cover the surface of this capacitor lower electrode and the upper surface of the core insulating film and a capacitor upper electrode formed so as to cover the surface of this core insulating film are provided so that the bottom surface of the core insulating film is positioned lower than the bottom surface of the capacitor lower electrode.
    Type: Application
    Filed: July 18, 2002
    Publication date: January 23, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akie Yutani
  • Publication number: 20020125524
    Abstract: A semiconductor device having a stacked capacitor is provided. A dielectric film (81) formed of BST by a sputtering process is entirely provided to cover upper part of a plurality of storage node electrodes (SN2). A dielectric film (82) formed of BST by a CVD process is entirely provided to cover the dielectric film (81). The dielectric films (81, 82) constitute a dielectric layer (80). A conductive layer made of platinum covers an entire surface of the dielectric film (82) to constitute a counter electrode (9) to the storage node electrodes. The dielectric layer has good step coverage, reduced dependence upon its underlying layer, and good crystallinity.
    Type: Application
    Filed: May 13, 2002
    Publication date: September 12, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tomonori Okudaira, Yoshikazu Tsunemine, Keiichiro Kashihara, Akie Yutani, Hiromi Itoh
  • Patent number: 6437968
    Abstract: An oxide dielectric film (7) is formed of barium strontium titanate to have a thickness of 300 to 600 Å, and a first platinum layer (81) is deposited thereon by, e.g., sputtering at a temperature not higher than 250° C. to have a thickness of 250 to 500 Å. Further, a second platinum layer (82) is deposited on the first platinum layer (81) by, e.g., sputtering at a temperature of 250 to 500° C. to have a thickness of 250 to 500 Å. Since the first platinum layer (81) has less grain boundary and is hard to connect to that of the second platinum layer (82), with less grain boundary diffusion caused, even if a hydrogen sintering of an aluminum interconnection layer (11) is performed, reduction species are unlikely to reach the oxide dielectric film (7) through the grain boundary. That suppresses deterioration of the oxide dielectric film (7) to avoid an increase of leak current therein.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: August 20, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akie Yutani
  • Patent number: 6344400
    Abstract: Referring to a capacitor having a capacitor dielectric film made of a high dielectric film, it is possible to obtain a method of manufacturing a semiconductor device capable of forming a fine storage node made of a noble metal. A polysilicon film is formed over a whole face of an interlayer insulating film (9), and is then subjected to anisotropic dry etching by using, as a mask, a resist having a predetermined opening pattern. Consequently, a polysilicon film (22a) is formed in contact with a plug layer (11). Next, a noble metal element is substituted for a silicon element contained in the polysilicon film (22a). Thus, it is possible to form a storage node (22) which has at least a surface made of the noble metal element and has the same three-dimensional configuration as the polysilicon film (22a) obtained before the substitution.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: February 5, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akie Yutani