Patents by Inventor Akiharu Miyanaga

Akiharu Miyanaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6184068
    Abstract: A process for fabricating a semiconductor device comprising the steps of: introducing into an amorphous silicon film, a metallic element which accelerates the crystallization of the amorphous silicon film; applying heat treatment to the amorphous silicon film to obtain a crystalline silicon film; irradiating a laser beam or an intense light to the crystalline silicon film; and heat treating the crystalline silicon film irradiated with a laser beam or an intense light.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: February 6, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Takeshi Fukunaga, Akiharu Miyanaga
  • Patent number: 6143661
    Abstract: A method of fabricating a semiconductor device by the use of laser crystallization steps is provided. During these crystallization steps, an amorphous or polycrystalline semiconductor is crystallized by laser irradiation in such a way that generation of ridges is suppressed. Two separate laser crystallization steps are carried out. First, a laser irradiation step is performed in a vacuum, using somewhat weak laser light. Then, another laser irradiation step is performed in a vacuum, in the atmosphere, or in an oxygen ambient with intenser laser light. The first laser irradiation conducted in a vacuum does not result in satisfactory crystallization. However, this irradiation can suppress generation of ridges. The second laser irradiation step is performed in a vacuum, in the atmosphere, or in an oxygen ambient to achieve sufficient crystallization, but no ridges are produced.
    Type: Grant
    Filed: August 13, 1998
    Date of Patent: November 7, 2000
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Takamasa Kousai, Hongyong Zhang, Akiharu Miyanaga
  • Patent number: 6144041
    Abstract: A method of manufacturing a semiconductor includes the steps of: forming a first semiconductor film on a substrate having an insulating surface; applying an energy to the first semiconductor film to crystallize the first semiconductor film; patterning the first semiconductor film to form a region that forms a seed crystal; etching the seed crystal to selectively leave a predetermined crystal face in the seed crystal; covering the seed crystal to form a second semiconductor film; and applying an energy to the second semiconductor film to conduct a crystal growth from the seed crystal in the second semiconductor film.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: November 7, 2000
    Assignee: Semiconductor Energy Laboratory, Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Satoshi Teramoto
  • Patent number: 6140165
    Abstract: In thin film transistors (TFTs) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate. Further, a gate insulating film and a gate electrode are formed. Impurities are introduced by a self-aligning process. Then, the laminate is annealed below the strain point of the substrate to activate the dopant impurities. On the other hand, Nickel or other element is also used as a catalytic element for promoting crystallization of an amorphous silicon film. First, this catalytic element is applied in contact with the surface of the amorphous silicon film. The film is heated at 450 to 650.degree. C. to create crystal nuclei. The film is further heated at a higher temperature to grow the crystal grains. In this way, a crystalline silicon film having improved crystallinity is formed.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: October 31, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura, Akiharu Miyanaga, Hisashi Ohtani
  • Patent number: 6133583
    Abstract: A film having a high thermal conductivity material such as aluminum nitride is formed on a substrate, and then a silicon film is formed. When a laser light or an intense light corresponding to the laser light is irradiated to the silicon film, since the aluminum nitride film absorbs heat, a portion of the silicon film near the aluminum nitride film is solidified immediately. However, since a solidifying speed is slow in another portion of the silicon film, crystallization progresses from the portion near the aluminum nitride film. When a substrate temperature is 400.degree. C. or higher at laser irradiation, since a solidifying speed is decreased, a crystallinity of the silicon film is increased. Also, when the substrate is thin, the crystallinity of the silicon film is increased.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: October 17, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasuhiko Takemura, Akiharu Miyanaga, Shunpei Yamazaki
  • Patent number: 6133073
    Abstract: The present invention is related to a thin film semiconductor which can be regarded as substantially a single crystal and a semiconductor device comprising an active layer formed by the thin film semiconductor. At least a concave or convex pattern is formed intentionally on a insulating film provided in contact with the lower surface of an amorphous silicon film, whereby at least a site is formed in which a metal element for accelerating crystallization can be segregated. Therefore, a crystal nuclei is selectively formed in a portion where the concave or convex pattern is located, which carries out controlling a crystal diameter. Thus, a crystalline silicon film is obtained. A crystallinity of the crystalline silicon film is improved by the irradiation of a laser light or an intense light having an energy equivalent to that of the laser light, whereby a monodomain region in which no grain boundary substantially exit is formed.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: October 17, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Jun Koyama, Takeshi Fukunaga
  • Patent number: 6110542
    Abstract: A method for forming a film by a plasma CVD process in which a high density plasma is generated in the presence of a magnetic field is described, characterized by that the electric power for generating the plasma has a pulsed waveform. The electric power typically is supplied by microwave, and the pulsed wave may be a complex wave having a two-step peak, or may be a complex wave obtained by complexing a pulsed wave with a stationary continuous wave of an electromagnetic wave having the same or different wavelength as that of the pulsed wave. The process enables deposition of a uniform film having an excellent adhesion to the substrate, at a reduced power consumption.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: August 29, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Tohru Inoue, Shunpei Yamazaki
  • Patent number: 6107639
    Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 .mu.m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: August 22, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
  • Patent number: 6093937
    Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and an active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of crystallization.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: July 25, 2000
    Assignee: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Akiharu Miyanaga, Takeshi Fukunaga
  • Patent number: 6087679
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: July 11, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Patent number: 6071766
    Abstract: An object of the present invention is to provide a technology of reducing a nickel element in the silicon film which is crystallized by using nickel. An extremely small amount of nickel is introduced into an amorphous silicon film which is formed on the glass substrate. Then this amorphous silicon film is crystallized by heating. At this time, the nickel element remains in the crystallized silicon film. Then an amorphous silicon film is formed on the surface of the silicon film crystallized with the action of nickel. Then the amorphous silicon film is further heat treated. By carrying out this heat treatment, the nickel element is dispersed from the crystallized silicon film into the amorphous silicon film with the result that the nickel density in the crystallized silicon film is lowered.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: June 6, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Akiharu Miyanaga, Satoshi Teramoto
  • Patent number: 6048758
    Abstract: A little amount of nickel is introduced into an amorphous silicon film formed on a glass substrate to crystallize the amorphous silicon film by heating. In this situation, nickel elements remain in a crystallized silicon film. An amorphous silicon film is formed on the surface of the crystallized silicon film and then subjected to a heat treatment. With this heat treatment, the nickel elements are diffused in the amorphous silicon film, thereby being capable of lowering the concentration of nickel in the crystallized silicon film.
    Type: Grant
    Filed: January 23, 1997
    Date of Patent: April 11, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Akiharu Miyanaga, Satoshi Teramoto
  • Patent number: 6037610
    Abstract: A semiconductor device having high carrier mobility, which comprises a substrate provided thereon a base film and further thereon a crystalline non-single crystal silicon film by crystal growth, wherein, the crystals are grown along the crystallographic [110] axis, and source/drain regions are provided approximately along the direction of carrier movement which coincides to the direction of crystal growth. Moreover, the electric conductivity along this direction of crystal growth is higher than any in other directions.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: March 14, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura, Akiharu Miyanaga, Hisashi Ohtani
  • Patent number: 6000696
    Abstract: A game machine enabled to make various responses by adding the psychosomatic state and emotion of the player as one of conditions for determining the responding manner. The psychosomatic state of the player is grasped to change the responses in accordance with the psychological state of the player by making use of both a chaos attractor obtained by numerically processing the information sampled from the player and the index indicating the degree how the chaos attractor matches the defining condition of the chaos.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: December 14, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toshiji Hamatani
  • Patent number: 5994172
    Abstract: A metal element density is lowered in a crystalline silicon film obtained by four hour treatment at about 550.degree. C. by using a catalyst metal which accelerates crystallization. At the same time, a crystalline silicon film can be obtained which has a high crystallinity. For this purpose, extremely oxide film 13 is formed on an amorphous silicon film formed on this glass substrate in the beginning. An aqueous solution of acetate added with 10 to 200 ppm (need adjustment) of catalyst element like nickel or the like is dripped. This state is held for a predetermined time. Then the spin drying is performed by using a spinner. The film is crystallized by four hour treatment at 550.degree. C. Then a localized nickel component is removed by the fluoric acid treatment. Further, the crystalline silicon film is obtained by laser light irradiation. Then a crystalline silicon film is obtained having a low density of metal element and a small defect density by four hour heat treatment at 550.degree. C.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: November 30, 1999
    Assignee: Semiconductor Energy Laboratory., Ltd.
    Inventors: Hisashi Ohtani, Takeshi Fukunaga, Akiharu Miyanaga
  • Patent number: 5986286
    Abstract: To provide a technology capable of promoting property of a thin film transistor formed on a glass substrate, a silicon oxide film 102 is formed on a glass substrate 101 and an amorphous silicon film 103 is formed thereon. A nickel acetate solution including nickel element that is a metal element promoting crystallization of silicon is coated and a water film 401 is formed. A state in which the nickel element is held in contact with the surface of the amorphous silicon film 103 is realized by performing spin drying. Uniform crystal growth is carried out as shown by arrow marks 104 by performing a heating treatment. An electrically inactive layer is formed by having nickel element having a high concentration which is present at front end portions of crystal growth react with an underlayer of the silicon oxide film 102. In this way the crystalline silicon film restraining the influence of nickel element can be provide.
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: November 16, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Satoshi Teramoto
  • Patent number: 5965904
    Abstract: The principle portion of a semiconductor device is made from a polycrystalline silicon semiconductor layer which yields an X ray diffraction pattern or an electron beam pattern with the (311) diffraction peak intensity accounting for 15% or more of the total diffraction peak intensity. A semiconductor device improved in performance and reliability can be obtained by reducing the density of states at the boundary between the polycrystalline silicon film and the gate insulating film.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: October 12, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Yasuhiko Takemura
  • Patent number: 5932893
    Abstract: An insulated gate field effect transistor comprises a silicon channel region. The silicon is crystallized by heat annealing while a suitable metal element such as nickel helps the crystallization. The crystallization proceeds in the silicon film laterally from the portion where the nickel is directly introduced. The TFT is arranged in such a manner that the source-drain direction of the TFT is aligned with the direction of the crystal growth or intersects with the crystal growth direction at a desired direction.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: August 3, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Hisashi Ohtani, Satoshi Teramoto
  • Patent number: 5923966
    Abstract: A laser processing apparatus provides a heating chamber, a chamber for laser light irradiation and a robot arm, wherein a temperature of a substrate on which a silicon film to be irradiated with laser light is formed is heated to 450 to 750.degree. C. in the heating chamber followed by irradiating the silicon film with laser light so that a silicon film having a single crystal or a silicon film that can be regarded as the single crystal can be obtained.
    Type: Grant
    Filed: July 20, 1995
    Date of Patent: July 13, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Teramoto, Hisashi Ohtani, Akiharu Miyanaga, Toshiji Hamatani, Shunpei Yamazaki
  • Patent number: 5923962
    Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: July 13, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Takeshi Fukunaga, Hongyong Zhang