Abstract: A phase locked loop has an integer phase detector to detect an integer phase by measuring a cycle number, a fractional phase detector to detect a fractional phase of smaller than one cycle between a reference signal and the oscillation signal, a frequency error generator to generate a frequency error signal between the reference signal and the oscillation signal, a glitch corrector to correct the frequency error signal to generate and output a glitch-corrected signal and the frequency error signal, a phase error generator to generate a phase error by integrating an output signal of the glitch corrector, an oscillator controller to control an oscillation frequency of the oscillation signal, and a synchronous detector to detect whether a phase of the reference signal and a phase of the oscillation signal are in an phase-lock state, and to stop detection of the integer phase when the phase-lock state is detected.

Abstract: A wireless communication apparatus has an analog control loop circuitry to generate an analog control signal which adjusts a phase of a voltage-controlled oscillation signal, an integrator to integrate the analog control signal, a phase adjuster to adjust a phase of the voltage-controlled oscillation signal, a digital control loop circuitry, in a first mode, to match a frequency of the voltage-controlled oscillation signal to a frequency of the received signal based on an output signal of the phase adjuster, and in a second mode, to generate a digital control signal which is opposite in phase to the analog control signal and has a frequency, a voltage-controlled oscillator to generate the voltage-controlled oscillation signal based on the analog and digital control signals, and a signal switch to supply the analog control signal to the integrator in the first mode and to the voltage-controlled oscillator in the second mode.

Abstract: According to an embodiment, a receiver includes a voltage controlled oscillator, a frequency-to-digital converter and an input sensitivity controller. In the voltage controlled oscillator, input sensitivity relative to a baseband signal is controlled based on an input sensitivity control signal. The voltage controlled oscillator oscillates at a frequency controlled by a voltage of the baseband signal to generate an oscillation signal. The frequency-to-digital converter performs frequency-to-digital conversion of the oscillation signal to generate a digital signal. The input sensitivity controller generates the input sensitivity control signal based on the digital signal.

Abstract: According to an embodiment, an auto frequency control circuit includes a peak time detector, a first time shifter a zero-crossing time detector, and a second time shifter. The peak time detector detects, from the digital signal, a first time at which the digital signal exhibits one of a maximal value and a minimal value. The first time shifter adds or subtracts a first natural number multiple of the predetermined period to or from the first time. The zero-crossing time detector detects, from the digital signal, a second time at which the digital signal exhibits one of a positive zero-crossing and a negative zero-crossing. The second time shifter adds or subtracts the first natural number multiple of the predetermined period to or from the second time.

Abstract: According to an embodiment, an auto frequency control circuit includes a peak time detector, a first time shifter a zero-crossing time detector, and a second time shifter. The peak time detector detects, from the digital signal, a first time at which the digital signal exhibits one of a maximal value and a minimal value. The first time shifter adds or subtracts a first natural number multiple of the predetermined period to or from the first time. The zero-crossing time detector detects, from the digital signal, a second time at which the digital signal exhibits one of a positive zero-crossing and a negative zero-crossing. The second time shifter adds or subtracts the first natural number multiple of the predetermined period to or from the second time.

Abstract: According to an embodiment, a receiver includes a voltage controlled oscillator, a frequency-to--digital converter and an input sensitivity controller. In the voltage controlled oscillator, input sensitivity relative to a baseband signal is controlled based on an input sensitivity control signal. The voltage controlled oscillator oscillates at a frequency controlled by a voltage of the baseband signal to generate an oscillation signal. . The frequency--to-digital converter performs frequency-to-digital conversion of the oscillation signal to generate a digital signal. The input sensitivity controller generates the input sensitivity control signal based on the digital signal.

Abstract: A wireless communication device has an analog control loop circuitry that generates an analog control signal to adjust a phase of a voltage controlled oscillation signal, in accordance with a phase of a reception signal, a digital control loop circuitry that generates a digital control signal having a frequency determined by a frequency of a reference signal and a predetermined frequency setting code signal and having a phase opposite to a phase of the analog control signal, a voltage controlled oscillator that generates the voltage controlled oscillation signal, on the basis of the analog control signal and the digital control signal, and a data slicer that generates a digital signal obtained by digital demodulation of the reception signal, on the basis of a comparison result of the digital control signal and a predetermined threshold value.

Abstract: In one embodiment, a current amplifier circuit includes a first transistor, a first resistor, a second transistor, a second resistor, a first passive element, and a control circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The first resistor has one end connected to the first terminal of the first transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The second resistor has one end connected to the first terminal of the second transistor. The first passive element is connected between the first terminals of the first transistor and the second transistor. The control circuit controls at least one of voltage at the control terminals of the first transistor and the second transistor such that the voltage at the other end of the first resistor becomes equal to the voltage at the other end of the second resistor.

Abstract: In one embodiment, an AD converter includes a first (second) oscillation circuit, a first (second) counter, a first (second) arithmetic circuit, a first (second) subtracting circuit, an adder circuit, and a feedback circuit. The first oscillation circuit generates a first pulse signal having a frequency corresponding to a level of a first analog signal. The first counter counts the first pulse signal. The first arithmetic circuit generates a first signal corresponding to a change amount of a count value. The first subtracting circuit outputs a digital signal corresponding to a difference between the signals generated by the first and second arithmetic circuits. The adder circuit generates a sum signal of the signals generated by the first and second arithmetic circuits. The second subtracting circuit generates a difference signal between the sum signal and a reference signal. The feedback circuit inputs the difference signal to the first oscillation circuit.

Abstract: In one embodiment, an AD converter includes a first (second) oscillation circuit, a first (second) counter, a first (second) arithmetic circuit, a first (second) subtracting circuit, an adder circuit, and a feedback circuit. The first oscillation circuit generates a first pulse signal having a frequency corresponding to a level of a first analog signal. The first counter counts the first pulse signal. The first arithmetic circuit generates a first signal corresponding to a change amount of a count value. The first subtracting circuit outputs a digital signal corresponding to a difference between the signals generated by the first and second arithmetic circuits. The adder circuit generates a sum signal of the signals generated by the first and second arithmetic circuits. The second subtracting circuit generates a difference signal between the sum signal and a reference signal. The feedback circuit inputs the difference signal to the first oscillation circuit.

Abstract: In one embodiment, a current amplifier circuit includes a first transistor, a first resistor, a second transistor, a second resistor, a first passive element, and a control circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The first resistor has one end connected to the first terminal of the first transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The second resistor has one end connected to the first terminal of the second transistor. The first passive element is connected between the first terminals of the first transistor and the second transistor. The control circuit controls at least one of voltage at the control terminals of the first transistor and the second transistor such that the voltage at the other end of the first resistor becomes equal to the voltage at the other end of the second resistor.

Abstract: According to one embodiment, a phase locked loop (PLL) circuit includes an application unit, a correlator, an integrator and a power supply noise canceller. The application unit applies the test signal to a power supply voltage. The correlator extracts a frequency error signal as a monitor signal and calculates a correlation value for the test signal and the monitor signal to generate a correlation signal. The integrator integrates the correlation signal to generate an integral signal. The power supply noise canceller provides a cancellation gain corresponding to the integral signal to the power supply voltage to which the test signal is applied, to generate a control signal.

Abstract: A phase locked loop circuit which obtains an output signal coincident in frequency and phase with a target signal which is acquired by multiplying the frequency of a reference signal by a ratio represented by the sum of a first fraction and a second fraction, the circuit includes a controlled oscillator including the same number of stages of annularly connected amplifiers as a number which is obtained by dividing, by 2, a least common multiple of a denominator of the first fraction, a denominator of the second fraction and 2, the same number of multiphase signals as the least common multiple being extractable from the controlled oscillator, the frequency of the multiphase signals being controlled by a digital control signal and an analog control signal, one of the multiphase signals being output as the output signal.

Abstract: According to one embodiment, a phase locked loop (PLL) circuit includes an application unit, a correlator, an integrator and a power supply noise canceller. The application unit applies the test signal to a power supply voltage. The correlator extracts a frequency error signal as a monitor signal and calculates a correlation value for the test signal and the monitor signal to generate a correlation signal. The integrator integrates the correlation signal to generate an integral signal. The power supply noise canceller provides a cancellation gain corresponding to the integral signal to the power supply voltage to which the test signal is applied, to generate a control signal.

Abstract: According to one embodiment, a register outputs a first control code in first and second operation modes, saves the first control code as a third control code at an end of the first operation mode, and outputs the third control code at a beginning of a third operation mode. In the first operation mode, a digital-to-analog converter supplies a control signal with a control voltage to a voltage controlled oscillator. In the second operation mode, the control signal is supplied to a buffer amplifier, the amplifier drives a bandlimiting filter, and the filter generates the control voltage. In the third operation mode, the control signal is supplied to the filter, and the filter generates the control voltage.

Abstract: There is provided an integrated circuit in which a reference-signal source generates a reference signal having a basic frequency, a phase locked loop includes a voltage-controlled oscillator, a first frequency divider to generate a first frequency-divided signal based on the signal by N, a phase detector, a charge pump and a loop filter, the second frequency generates a second frequency-divided signal based on the signal generated by the voltage-controlled oscillator by M, wherein a minimum absolute value of a difference between the basic frequency multiplied by “K” and a frequency of the second frequency-divided signal is equal to or less than a low cutoff frequency of a bandpass filter or equal to or higher than a high cutoff frequency of the bandpass filter, the bandpass filter being represented by a transfer function from an input of the voltage-controlled oscillator to an output of the phase locked loop.

Abstract: There is provided an integrated circuit in which a reference-signal source generates a reference signal having a basic frequency, a phase locked loop includes a voltage-controlled oscillator, a first frequency divider to generate a first frequency-divided signal based on the signal by N, a phase detector, a charge pump and a loop filter, the second frequency generates a second frequency-divided signal based on the signal generated by the voltage-controlled oscillator by M, wherein a minimum absolute value of a difference between the basic frequency multiplied by “K” and a frequency of the second frequency-divided signal is equal to or less than a low cutoff frequency of a bandpass filter or equal to or higher than a high cutoff frequency of the bandpass filter, the bandpass filter being represented by a transfer function from an input of the voltage-controlled oscillator to an output of the phase locked loop.

Abstract: According to one embodiment, a register outputs a first control code in first and second operation modes, saves the first control code as a third control code at an end of the first operation mode, and outputs the third control code at a beginning of a third operation mode. In the first operation mode, a digital-to-analog converter supplies a control signal with a control voltage to a voltage controlled oscillator. In the second operation mode, the control signal is supplied to a buffer amplifier, the amplifier drives a bandlimiting filter, and the filter generates the control voltage. In the third operation mode, the control signal is supplied to the filter, and the filter generates the control voltage.

Abstract: The voltage-controlled oscillator generates a first signal and a second signal having a phase reverse to that of the first signal, frequencies thereof being controlled depending on control voltages. The sub-sampling phase comparator generates first/second sampled voltages by sampling voltages of the first/second signals in each cycle of the reference signal having cycles. The current generating circuit has first/second charge pumps configured to generate first/second current signal depending on supply voltages, the second current signal having a polarity reverse to that of the first current signal. The selection controller selectively carries out a first supply mode for supplying the first and second sampled voltages to the second and first charge pumps and a second supply mode for supplying the first and second sampled voltages to the first and second charge pumps respectively.

Abstract: The voltage-controlled oscillator generates a first signal and a second signal having a phase reverse to that of the first signal, frequencies thereof being controlled depending on control voltages. The sub-sampling phase comparator generates first/second sampled voltages by sampling voltages of the first/second signals in each cycle of the reference signal having cycles. The current generating circuit has first/second charge pumps configured to generate first/second current signal depending on supply voltages, the second current signal having a polarity reverse to that of the first current signal. The selection controller selectively carries out a first supply mode for supplying the first and second sampled voltages to the second and first charge pumps and a second supply mode for supplying the first and second sampled voltages to the first and second charge pumps respectively.