Patents by Inventor Akihiko Happoya

Akihiko Happoya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220130644
    Abstract: A plasma processing apparatus includes: a chamber including a first member, and a second member detachable from the first member; a conductive member disposed between the first member and the second member; and a first high frequency power supply generating plasma in the chamber. The conductive member includes a resin member made of a resin material, and a metal film covering a surface of the resin member.
    Type: Application
    Filed: March 13, 2020
    Publication date: April 28, 2022
    Applicants: Noa Leading Co., Ltd., TOSHIBA MATERIALS CO., LTD.
    Inventors: Masahiro YOKOTA, Akihiko HAPPOYA, Ken TAKAHASHI, Shusuke MORITA, Jiro OSHIMA, Shuichi SAITO, Noriaki YAGI, Atsuya SASAKI
  • Patent number: 10673125
    Abstract: According to an embodiment, a wireless apparatus includes an interposer including a conductive portion; a semiconductor chip mounted on a component mounting surface of the interposer; a sealing resin on the component mounting surface and sealing the semiconductor chip; a conductive layer covering a surface of the sealing resin and a side surface of the interposer and electrically connected to the conductive portion; a first slot-shaped aperture on a principal surface portion of the conductive layer facing the component mounting surface; a second slot-shaped aperture on a side surface portion of the conductive layer facing the side surface and continuing to the first aperture; and a slot-shaped aperture at the conductive portion and continuing to the second aperture. The first to third apertures function as an integrated slot antenna. A total length of the first aperture is longer than a total length of the third aperture.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: June 2, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiju Yamada, Makoto Sano, Makoto Higaki, Koh Hashimoto, Akihiko Happoya
  • Publication number: 20190288375
    Abstract: According to an embodiment, a wireless apparatus includes an interposer including a conductive portion; a semiconductor chip mounted on a component mounting surface of the interposer; a sealing resin on the component mounting surface and sealing the semiconductor chip; a conductive layer covering a surface of the sealing resin and a side surface of the interposer and electrically connected to the conductive portion; a first slot-shaped aperture on a principal surface portion of the conductive layer facing the component mounting surface; a second slot-shaped aperture on a side surface portion of the conductive layer facing the side surface and continuing to the first aperture; and a slot-shaped aperture at the conductive portion and continuing to the second aperture. The first to third apertures function as an integrated slot antenna. A total length of the first aperture is longer than a total length of the third aperture.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju YAMADA, Makoto Sano, Makoto Higaki, Koh Hashimoto, Akihiko Happoya
  • Patent number: 10355338
    Abstract: According to an embodiment, a wireless apparatus includes an interposer including a conductive portion; a semiconductor chip mounted on a component mounting surface of the interposer; a sealing resin on the component mounting surface and sealing the semiconductor chip; a conductive layer covering a surface of the sealing resin and a side surface of the interposer and electrically connected to the conductive portion; a first slot-shaped aperture on a principal surface portion of the conductive layer facing the component mounting surface; a second slot-shaped aperture on a side surface portion of the conductive layer facing the side surface and continuing to the first aperture; and a slot-shaped aperture at the conductive portion and continuing to the second aperture. The first to third apertures function as an integrated slot antenna. A total length of the first aperture is longer than a total length of the third aperture.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 16, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiju Yamada, Makoto Sano, Makoto Higaki, Koh Hashimoto, Akihiko Happoya
  • Publication number: 20190198421
    Abstract: According to one embodiment, a heat radiating plate-lined ceramic substrate includes a first bonding layer, a plating layer and a heat radiating plate provided in order on the ceramic substrate. The first bonding layer is formed from a molecular bonding material containing a ceramic substrate fixing portion and a plating support portion. The ceramic substrate fixing portion and the first bonding layer are bonded together by the ceramic substrate fixing portion and the plating layer and the first bonding layer are bonded together by the plating support portion.
    Type: Application
    Filed: March 14, 2018
    Publication date: June 27, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro Yokota, Akihiko Happoya
  • Patent number: 10249531
    Abstract: A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group; forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer; patterning the second insulating layer to form a mask pattern; etching the first insulating layer by a wet etching method; selectively forming a catalyst layer; and forming a metal layer on the catalyst layer by an electroless plating method.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: April 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Atsushi Hieno, Tsutomu Nakanishi, Yusuke Tanaka, Yasuhito Yoshimizu, Akihiko Happoya
  • Publication number: 20190088539
    Abstract: A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group; forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer; patterning the second insulating layer to form a mask pattern; etching the first insulating layer by a wet etching method; selectively forming a catalyst layer; and forming a metal layer on the catalyst layer by an electroless plating method.
    Type: Application
    Filed: February 9, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Atsushi Hieno, Tsutomu Nakanishi, Yusuke Tanaka, Yasuhito Yoshimizu, Akihiko Happoya
  • Patent number: 10163765
    Abstract: A semiconductor device includes a semiconductor chip having a terminal thereon, a lead frame for connection to an external device, a bonding wire connecting the terminal of the semiconductor chip and the lead frame. A mold resin layer encloses the semiconductor chip and the bonding wire, such that a portion of the lead frame extends out of the mold resin layer. A molecular bonding layer has a portion on a surface of the bonding wire and includes a first molecular portion covalently bonded to a material of the bonding wire and a material of the mold resin layer.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihiko Happoya
  • Patent number: 10147612
    Abstract: A metal pattern forming method according to an embodiment includes forming a metal film on a surface of a substrate by an electroless plating method, the substrate including a first layer including a protrusion and a recess, and a film thickness of the metal film being a half or more of a width of the recess; and performing wet etching, the metal film in the recess removed by the wet etching and the metal film on the protrusion remained after the wet etching.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 4, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Nakanishi, Yusuke Tanaka, Atsushi Hieno, Yasuhito Yoshimizu, Akihiko Happoya
  • Publication number: 20180277390
    Abstract: A metal pattern forming method according to an embodiment includes forming a metal film on a surface of a substrate by an electroless plating method, the substrate including a first layer including a protrusion and a recess, and a film thickness of the metal film being a half or more of a width of the recess; and performing wet etching, the metal film in the recess removed by the wet etching and the metal film on the protrusion remained after the wet etching.
    Type: Application
    Filed: August 28, 2017
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu NAKANISHI, Yusuke Tanaka, Atsushi Hieno, Yasuhito Yoshimizu, Akihiko Happoya
  • Publication number: 20180274102
    Abstract: A method of forming a metal pattern includes forming a catalyst adsorption layer by bringing a surface of a substrate into contact with a solution, the substrate having a base region and a plurality of protrusions provided on the base region, the base region includes a first material, the protrusions includes a second material different from the first material, the first and the second material being exposed on the surface, and the solution containing a compound having a triazine skeleton, a first functional group of any one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, and an azido group, forming a catalyst layer on the catalyst adsorption layer, forming a metal film on the catalyst layer by an electroless plating method, and removing the metal film on the protrusions.
    Type: Application
    Filed: September 7, 2017
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke TANAKA, Atsushi HIENO, Tsutomu NAKANISHI, Yasuhito YOSHIMIZU, Akihiko HAPPOYA
  • Publication number: 20180053987
    Abstract: According to an embodiment, a wireless apparatus includes an interposer including a conductive portion; a semiconductor chip mounted on a component mounting surface of the interposer; a sealing resin on the component mounting surface and sealing the semiconductor chip; a conductive layer covering a surface of the sealing resin and a side surface of the interposer and electrically connected to the conductive portion; a first slot-shaped aperture on a principal surface portion of the conductive layer facing the component mounting surface; a second slot-shaped aperture on a side surface portion of the conductive layer facing the side surface and continuing to the first aperture; and a slot-shaped aperture at the conductive portion and continuing to the second aperture. The first to third apertures function as an integrated slot antenna. A total length of the first aperture is longer than a total length of the third aperture.
    Type: Application
    Filed: February 24, 2017
    Publication date: February 22, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju YAMADA, Makoto SANO, Makoto HIGAKI, Koh HASHIMOTO, Akihiko HAPPOYA
  • Publication number: 20170301615
    Abstract: A semiconductor device includes a semiconductor chip having a terminal thereon, a lead frame for connection to an external device, a bonding wire connecting the terminal of the semiconductor chip and the lead frame. A mold resin layer encloses the semiconductor chip and the bonding wire, such that a portion of the lead frame extends out of the mold resin layer. A molecular bonding layer has a portion on a surface of the bonding wire and includes a first molecular portion covalently bonded to a material of the bonding wire and a material of the mold resin layer.
    Type: Application
    Filed: February 23, 2017
    Publication date: October 19, 2017
    Inventor: Akihiko HAPPOYA
  • Patent number: 9793202
    Abstract: According to an embodiment, a wireless apparatus includes an interposer substrate, a semiconductor chip, a nonconductive layer, and a conductive film. The interposer substrate includes a conductive portion. The semiconductor chip is mounted on a component mounting face of the interposer substrate. The nonconductive layer is provided on the component mounting face to seal the chip. The conductive film is configured to cover a surface of the nonconductive layer and a side of the interposer substrate and is electrically connected to the conductive portion. The film has a first slot aperture. The conductive portion has a second slot aperture connecting to the first slot aperture. The first and second slot apertures serve as an integrated slot antenna. The antenna has first and second portions. The first portion includes a boundary between the first and second slot apertures and has a width larger than a width of the second portion.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: October 17, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koh Hashimoto, Makoto Sano, Keiju Yamada, Makoto Higaki, Akihiko Happoya
  • Publication number: 20170294408
    Abstract: A semiconductor device includes a semiconductor chip covered with a resin layer, the semiconductor chip including an electrode pad at a surface of the semiconductor chop, a first insulating layer covering the surface of the semiconductor chip and having a via hole at a region corresponding to the electrode pad, a conductive layer extending along a surface of the electrode pad, a side surface of the via hole, and a planar surface the first insulating layer to a region beyond a planar region defined by the semiconductor chip. A molecular bonding layer is between the first insulating layer and the conductive layer and includes a molecular portion covalently bonded to a material of the first insulating layer and a material of the first insulating layer. A second insulating layer is on the first insulating layer and covering the conductive layer.
    Type: Application
    Filed: February 24, 2017
    Publication date: October 12, 2017
    Inventor: Akihiko HAPPOYA
  • Publication number: 20170294394
    Abstract: A semiconductor device includes a substrate including, on a surface thereof, a first conductive pad and a first insulating layer formed around the first conductive pad, a semiconductor chip including, on a surface thereof, a second conductive pad and a second insulating layer around the second conductive pad, an intermediate layer formed between the substrate and the semiconductor chip, and including a conductive portion between the first and second conductive pads, and an insulating portion between the first and second insulating layers, and a molecular bonding layer formed between the substrate and the intermediate layer, and including at least one of a first molecular portion covalently bonded to a material of the first conductive pad and a material of the conductive portion, and a second molecular portion covalently bonded to a material of the first insulating layer and a material of the insulating portion.
    Type: Application
    Filed: February 24, 2017
    Publication date: October 12, 2017
    Inventors: Daigo SUZUKI, Akihiko HAPPOYA
  • Publication number: 20170294395
    Abstract: A semiconductor device includes a base, a semiconductor chip on the base, a conductive bonding layer between a surface of the base and a surface of the semiconductor chip, the conductive bonding layer including a resin and a plurality of conductive particles contained in the resin, and a molecular bonding layer between the surface of the semiconductor chip and a surface of the conductive bonding layer, and including a molecular portion covalently bonded to a material of the semiconductor chip and a material of the conductive bonding layer.
    Type: Application
    Filed: February 24, 2017
    Publication date: October 12, 2017
    Inventor: Akihiko HAPPOYA
  • Publication number: 20170294398
    Abstract: A semiconductor device includes a semiconductor chip covered with a resin layer, the semiconductor chip including an electrode pad at a surface of the semiconductor chip, a first insulating layer covering the surface of the semiconductor chip and having a via hole at a region corresponding to the electrode pad, a conductive layer extending along a surface of the electrode pad, a side surface of the via hole, and a planar surface the first insulating layer, to a region beyond a planar region defined by the semiconductor chip, a second insulating layer on the first insulating layer and covering the conductive layer; and a molecular bonding layer formed between the first insulating layer and the second insulating layer and including a molecular portion covalently bonded to a material of the conductive layer and a material of the second insulating layer.
    Type: Application
    Filed: February 23, 2017
    Publication date: October 12, 2017
    Inventor: Akihiko HAPPOYA
  • Patent number: 9595646
    Abstract: According to one embodiment, an electronic component includes a metal portion, a mold resin covering at least a part of the metal portion, and a molecular adhesion layer provided between a surface of the metal portion and the mold resin.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: March 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiko Happoya, Daigo Suzuki
  • Patent number: 9431588
    Abstract: Provided is an optical semiconductor device includes: a light-emitting layer having a first main surface, a second main surface opposed to the first main surface, a first electrode and a second electrode which are formed on the second main surface; a fluorescent layer provided on the first main surface; a light-transmissive layer provided on the fluorescent layer and made of a light-transmissive inorganic material; a first metal post provided on the first electrode; a second metal post provided on the second electrode; a sealing layer provided on the second main surface so as to seal in the first and second metal posts with one ends of the respective first and second metal posts exposed; a first metal layer provided on the exposed end of the first metal post; and a second metal layer provided on the exposed end of the second metal post.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: August 30, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Takeshi Miyagi, Akihiko Happoya, Kazuhito Higuchi, Tomoyuki Kitani