Patents by Inventor Akihiko Happoya

Akihiko Happoya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160216728
    Abstract: An electronic device includes an insulating layer, a first conductor portion disposed in the insulating layer, a second conductor portion disposed on a surface of the insulating layer, and a wiring member disposed within the insulating layer and electrically connecting the first conductor portion and the second conductor portion. The wiring member includes a connection portion welded to the first conductor portion and an extension portion extending from the connection portion to the second conductor portion.
    Type: Application
    Filed: August 25, 2015
    Publication date: July 28, 2016
    Inventors: Akihiko HAPPOYA, Yoshikazu FURUMIYA
  • Publication number: 20160157392
    Abstract: An electronic device module includes an electronic unit, a sealing layer covering the electronic unit and containing organic molecules, a shield layer covering the sealing layer and containing inorganic elements on an inner surface thereof, and a bonding layer formed between the sealing layer and the shield layer, and containing molecules that are chemically bonded with the organic molecules of the sealing layer and the inorganic elements of the shield layer.
    Type: Application
    Filed: August 10, 2015
    Publication date: June 2, 2016
    Inventor: Akihiko HAPPOYA
  • Publication number: 20160150133
    Abstract: An electronic device module includes a substrate, an imaging unit disposed on the substrate and electrically connected thereto, a resin member disposed on the substrate and covering an peripheral region of the imaging unit, a lens unit disposed above the imaging unit, and a frame having a portion that is disposed on a top surface of the resin member and supports the lens unit.
    Type: Application
    Filed: August 10, 2015
    Publication date: May 26, 2016
    Inventors: Daigo SUZUKI, Akihiko HAPPOYA, Jun OOTSUBO, Fongru LIN
  • Publication number: 20160143150
    Abstract: A method for manufacturing a flexible printed circuit module includes discharging an insulating material from an inkjet head towards a surface of a flexible printed circuit board, such that an electrode on the surface of the flexible printed circuit board is exposed, and curing the insulating material to be formed.
    Type: Application
    Filed: September 1, 2015
    Publication date: May 19, 2016
    Inventors: Akihiko HAPPOYA, Kota TOKUDA
  • Patent number: 9345134
    Abstract: According to one embodiment, a printed wiring board includes a circuit board, a ground pattern provided on the circuit board, a wiring pattern provided on the circuit board, a conductive reinforcing plate covering the ground pattern and the wiring pattern and electrically connected with the ground pattern, and an insulating portion provided between the conductive reinforcing plate and the wiring pattern.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: May 17, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiko Happoya, Daigo Suzuki
  • Publication number: 20160073495
    Abstract: A method for manufacturing a flexible printed circuit module, includes discharging an adhesive material from an inkjet head towards one or more target regions of a flexible printed circuit board, semi-curing the adhesive material on the flexible printed circuit board, placing one or more reinforcement members on a surface of the adhesive material, and pressing the one or more reinforcement members against the flexible printed circuit board while heating the adhesive material, such that the one or more reinforcement members are fixed on the flexible printed circuit board.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 10, 2016
    Inventors: Akihiko HAPPOYA, Kota TOKUDA
  • Publication number: 20160035948
    Abstract: According to one embodiment, an electronic component includes a metal portion, a mold resin covering at least a part of the metal portion, and a molecular adhesion layer provided between a surface of the metal portion and the mold resin.
    Type: Application
    Filed: December 9, 2014
    Publication date: February 4, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiko HAPPOYA, Daigo SUZUKI
  • Publication number: 20150366069
    Abstract: According to one embodiment, an apparatus includes: a device configured to partially provide a second conductor layer on a surface of a first conductor layer; a device configured to partially provide a first insulating layer on the surface of the first conductor layer; a device configured to integrate the first conductor layer, the second conductor layer, the first insulating layer, and a third conductor layer, in a state in which the second conductor layer and the first insulating layer provided on the surface of the first conductor layer are covered with the third conductor layer from a side opposite the first conductor layer; a device configured to form a conductor pattern by partially removing at least one of the first conductor layer and the third conductor layer in a structure obtained by the integrating; and a device configured to cover both sides of the structure.
    Type: Application
    Filed: August 26, 2015
    Publication date: December 17, 2015
    Inventors: Akihiko Happoya, Yasuki Torigoshi, Sadahiro Tamai
  • Patent number: 9155203
    Abstract: According to one embodiment, an apparatus includes: a device configured to partially provide a second conductor layer on a surface of a first conductor layer; a device configured to partially provide a first insulating layer on the surface of the first conductor layer; a device configured to integrate the first conductor layer, the second conductor layer, the first insulating layer, and a third conductor layer, in a state in which the second conductor layer and the first insulating layer provided on the surface of the first conductor layer are covered with the third conductor layer from a side opposite the first conductor layer; a device configured to form a conductor pattern by partially removing at least one of the first conductor layer and the third conductor layer in a structure obtained by the integrating; and a device configured to cover both sides of the structure.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiko Happoya, Yasuki Torigoshi, Sadahiro Tamai
  • Publication number: 20150264797
    Abstract: An electronic apparatus includes a first substrate, an electronic component mounted on a first surface of the first substrate, a plurality of first lands on a second surface of the first substrate that is opposite the first surface, the first lands electrically connected to the electronic component and arranged at a first interval, and a plurality of second lands on the second surface of the first substrate and surrounding the first lands, the second lands arranged at a second interval that is smaller than the first interval.
    Type: Application
    Filed: July 29, 2014
    Publication date: September 17, 2015
    Inventors: Akihiko HAPPOYA, Yuichi SATO, Daigo SUZUKI
  • Publication number: 20150264290
    Abstract: A camera module includes a metal plate including a recessed portion, a flexible printed board having a portion that is accommodated in the recessed portion, an image sensor arranged on the portion of the printed board accommodated in the recessed portion, and a case including a lens for guiding light to the image sensor.
    Type: Application
    Filed: July 29, 2014
    Publication date: September 17, 2015
    Inventors: Akihiko HAPPOYA, Daigo SUZUKI
  • Publication number: 20150264806
    Abstract: According to one embodiment, a printed wiring board includes a circuit board, a ground pattern provided on the circuit board, a wiring pattern provided on the circuit board, a conductive reinforcing plate covering the ground pattern and the wiring pattern and electrically connected with the ground pattern, and an insulating portion provided between the conductive reinforcing plate and the wiring pattern.
    Type: Application
    Filed: July 18, 2014
    Publication date: September 17, 2015
    Inventors: Akihiko HAPPOYA, Daigo SUZUKI
  • Publication number: 20150001571
    Abstract: Provided is an optical semiconductor device includes: a light-emitting layer having a first main surface, a second main surface opposed to the first main surface, a first electrode and a second electrode which are formed on the second main surface; a fluorescent layer provided on the first main surface; a light-transmissive layer provided on the fluorescent layer and made of a light-transmissive inorganic material; a first metal post provided on the first electrode; a second metal post provided on the second electrode; a sealing layer provided on the second main surface so as to seal in the first and second metal posts with one ends of the respective first and second metal posts exposed; a first metal layer provided on the exposed end of the first metal post; and a second metal layer provided on the exposed end of the second metal post.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuo SHIMOKAWA, Takashi Koyanagawa, Takeshi Miyagi, Akihiko Happoya, Kazuhito Higuchi, Tomoyuki Kitani
  • Patent number: 8906716
    Abstract: Provided is an optical semiconductor device includes: a light-emitting layer having a first main surface, a second main surface opposed to the first main surface, a first electrode and a second electrode which are formed on the second main surface; a fluorescent layer provided on the first main surface; a light-transmissive layer provided on the fluorescent layer and made of a light-transmissive inorganic material; a first metal post provided on the first electrode; a second metal post provided on the second electrode; a sealing layer provided on the second main surface so as to seal in the first and second metal posts with one ends of the respective first and second metal posts exposed; a first metal layer provided on the exposed end of the first metal post; and a second metal layer provided on the exposed end of the second metal post.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Takeshi Miyagi, Akihiko Happoya, Kazuhito Higuchi, Tomoyuki Kitani
  • Patent number: 8896761
    Abstract: According to one embodiment, a television receiver includes: a housing; a circuit board; a flexible printed wiring board comprising a base layer, a conductive layer, and a protective layer. The circuit board is installed in the housing. The flexible printed wiring board is configured to be electrically connected to the circuit board. The base layer includes a first surface and a second surface positioned on an opposite side of the first surface. The conductive layer is provided on at least one of the first surface and the second surface of the base layer. The protective layer is configured to cover the base layer and the conductive layer, and includes an outer edge portion positioned on an outside of a periphery portion of the base layer.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiko Happoya, Gen Fukaya
  • Publication number: 20140322841
    Abstract: According to an aspect of the invention, there is provided a light emitting element module substrate including: a laminated plate; and a metal layer. The laminated plate includes a base metal plate and an insulating layer provided on the base metal plate. The metal layer is provided on the insulating layer. The metal layer includes a mounting section on which a light emitting element is to be mounted, and a bonding section to which a wiring electrically connected to the light emitting element is to be bonded. The metal layer includes a silver layer which is an uppermost layer of at least one of the mounting section and the bonding section and is formed by electrolytic plating. The mounting section and the bonding section are electrically isolated from a periphery of the laminated plate.
    Type: Application
    Filed: July 11, 2014
    Publication date: October 30, 2014
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Lighting & Technology Corporation
    Inventors: Akihiko HAPPOYA, Masahiro Izumi, Tomohiro Sanpei
  • Patent number: 8742264
    Abstract: According to one embodiment, an electronic apparatus includes a housing and a flexible printed wiring board in the housing. The flexible printed wiring board includes a via, an insulator, a first conductive pattern, and a second conductive pattern. The insulator around the via includes a first surface and a second surface opposite to the first surface. The first conductive pattern is connected to the via on the first surface. The second conductive pattern is connected to the via on the second surface.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiko Happoya, Yasuki Torigoshi, Sadahiro Tamai
  • Publication number: 20140008688
    Abstract: Provided is an optical semiconductor device includes: a light-emitting layer having a first main surface, a second main surface opposed to the first main surface, a first electrode and a second electrode which are formed on the second main surface; a fluorescent layer provided on the first main surface; a light-transmissive layer provided on the fluorescent layer and made of a light-transmissive inorganic material; a first metal post provided on the first electrode; a second metal post provided on the second electrode; a sealing layer provided on the second main surface so as to seal in the first and second metal posts with one ends of the respective first and second metal posts exposed; a first metal layer provided on the exposed end of the first metal post; and a second metal layer provided on the exposed end of the second metal post.
    Type: Application
    Filed: September 11, 2013
    Publication date: January 9, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Takeshi Miyagi, Akihiko Happoya, Kazuhito Higuchi, Tomoyuki Kitani
  • Patent number: 8581291
    Abstract: Provided is an optical semiconductor device includes: a light-emitting layer having a first main surface, a second main surface opposed to the first main surface, a first electrode and a second electrode which are formed on the second main surface; a fluorescent layer provided on the first main surface; a light-transmissive layer provided on the fluorescent layer and made of a light-transmissive inorganic material; a first metal post provided on the first electrode; a second metal post provided on the second electrode; a sealing layer provided on the second main surface so as to seal in the first and second metal posts with one ends of the respective first and second metal posts exposed; a first metal layer provided on the exposed end of the first metal post; and a second metal layer provided on the exposed end of the second metal post.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Takeshi Miyagi, Akihiko Happoya, Kazuhito Higuchi, Tomoyuki Kitani
  • Publication number: 20130081568
    Abstract: According to one embodiment, an apparatus includes: a device configured to partially provide a second conductor layer on a surface of a first conductor layer; a device configured to partially provide a first insulating layer on the surface of the first conductor layer; a device configured to integrate the first conductor layer, the second conductor layer, the first insulating layer, and a third conductor layer, in a state in which the second conductor layer and the first insulating layer provided on the surface of the first conductor layer are covered with the third conductor layer from a side opposite the first conductor layer; a device configured to form a conductor pattern by partially removing at least one of the first conductor layer and the third conductor layer in a structure obtained by the integrating; and a device configured to cover both sides of the structure.
    Type: Application
    Filed: May 3, 2012
    Publication date: April 4, 2013
    Inventors: Akihiko Happoya, Yasuki Torigoshi, Sadahiro Tamai