Patents by Inventor Akihiko Kameoka
Akihiko Kameoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240091342Abstract: Provided is an orally administrable vaccine against a coronavirus infectious disease. A transformed Bifidobacterium designed to display a part or a whole of a constituent protein of a coronavirus on a surface of the Bifidobacterium enables the provision of the orally administrable vaccine against a coronavirus infectious disease. The transformed Bifidobacterium designed to display a part or a whole of a constituent protein of a coronavirus on a surface of the Bifidobacterium can induce humoral immunity and cellular immunity through oral administration to suppress an increase in severity of pneumonia or the like even after viral infection.Type: ApplicationFiled: January 25, 2022Publication date: March 21, 2024Applicants: NATIONAL UNIVERSITY CORPORATION KOBE UNIVERSITY, Kyoto UniversityInventors: Toshiro SHIRAKAWA, Shunpei UENO, Koichi KITAGAWA, Akihiko KONDO, Masanori KAMEOKA, Takane KATAYAMA
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Patent number: 7998795Abstract: A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively. the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.Type: GrantFiled: June 17, 2010Date of Patent: August 16, 2011Assignee: Renesas Electronics CorporationInventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Noriaki Sakamoto
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Patent number: 7989267Abstract: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes in the atmosphere which has oxygen, crosslinkage density becoming high in resin of adhesives, a low molecular compound volatilizes and jumps out outside, therefore as a result, since a low molecular compound does not remain in resin of adhesives, the generation of copper migration can be prevented.Type: GrantFiled: April 16, 2008Date of Patent: August 2, 2011Assignee: Renesas Electronics CorporationInventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Junpei Kusukawa, Yoshitaka Takezawa
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Publication number: 20100255639Abstract: A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively, the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.Type: ApplicationFiled: June 17, 2010Publication date: October 7, 2010Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Noriaki Sakamoto
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Patent number: 7772044Abstract: A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively. the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.Type: GrantFiled: November 3, 2008Date of Patent: August 10, 2010Assignee: Renesas Technology Corp.Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Noriaki Sakamoto
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Patent number: 7678706Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.Type: GrantFiled: July 20, 2007Date of Patent: March 16, 2010Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Publication number: 20090061563Abstract: A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively. the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.Type: ApplicationFiled: November 3, 2008Publication date: March 5, 2009Inventors: Fujio ITO, Hiromichi SUZUKI, Akihiko KAMEOKA, Noriaki SAKAMOTO
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Patent number: 7466024Abstract: A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.Type: GrantFiled: October 16, 2006Date of Patent: December 16, 2008Assignee: Renesas Technology Corp.Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Noriaki Sakamoto
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Publication number: 20080199987Abstract: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes in the atmosphere which has oxygen, crosslinkage density becoming high in resin of adhesives, a low molecular compound volatilizes and jumps out outside, therefore as a result, since a low molecular compound does not remain in resin of adhesives, the generation of copper migration can be prevented.Type: ApplicationFiled: April 16, 2008Publication date: August 21, 2008Inventors: Fujio ITO, Hiromichi Suzuki, Akihiko Kameoka, Junpei Kusukawa, Yoshitaka Takezawa
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Patent number: 7374973Abstract: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes in the atmosphere which has oxygen, crosslinkage density becoming high in resin of adhesives, a low molecular compound volatilizes and jumps out outside, therefore as a result, since a low molecular compound does not remain in resin of adhesives, the generation of copper migration can be prevented.Type: GrantFiled: July 15, 2005Date of Patent: May 20, 2008Assignee: Renesas Technology Corp.Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Junpei Kusukawa, Yoshitaka Takezawa
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Publication number: 20070298545Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.Type: ApplicationFiled: July 20, 2007Publication date: December 27, 2007Inventors: Yoshinori MIYAKI, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Patent number: 7247576Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.Type: GrantFiled: October 28, 2005Date of Patent: July 24, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Patent number: 7199469Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.Type: GrantFiled: September 28, 2001Date of Patent: April 3, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Toru Ishida, Tetsuharu Urawa, Fujio Ito, Tomoo Matsuzawa, Kazunari Suzuki, Akihiko Kameoka, Hiromichi Suzuki, Takuji Ide
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Publication number: 20070035017Abstract: A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.Type: ApplicationFiled: October 16, 2006Publication date: February 15, 2007Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Noriaki Sakamoto
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Publication number: 20060199302Abstract: A semiconductor device is manufactured by adhering a fixing tape to plural leads of a lead frame comprising a copper alloy, mounting a semiconductor chip on a tab of the lead frame, electrically connecting the leads to electrodes a of the semiconductor chip via bonding wires, forming a sealing resin portion that seals the semiconductor chip, the tab, the bonding wires, the leads and the fixing tape, and cutting the lead frame. A binder layer of the fixing tape includes at least % by weight of an amine-curable epoxy resin as its main component, and does not include a phenol resin. The binder layer of the fixing tape further includes no more than % by weight of acrylonitrile butadiene rubber. By using this material for the binder layer of the fixing tape, migration of the copper in the leads is suppressed even when a degradation test with strict environmental degradation conditions is conducted.Type: ApplicationFiled: March 6, 2006Publication date: September 7, 2006Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Yoshitaka Takezawa, Junpei Kusukawa
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Publication number: 20060049499Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.Type: ApplicationFiled: October 28, 2005Publication date: March 9, 2006Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Patent number: 6989334Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.Type: GrantFiled: May 15, 2003Date of Patent: January 24, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Publication number: 20060014321Abstract: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes in the atmosphere which has oxygen, crosslinkage density becoming high in resin of adhesives, a low molecular compound volatilizes and jumps out outside, therefore as a result, since a low molecular compound does not remain in resin of adhesives, the generation of copper migration can be prevented.Type: ApplicationFiled: July 15, 2005Publication date: January 19, 2006Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Junpei Kusukawa, Yoshitaka Takezawa
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Publication number: 20050230793Abstract: A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.Type: ApplicationFiled: April 15, 2005Publication date: October 20, 2005Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Noriaki Sakamoto
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Patent number: 6943456Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.Type: GrantFiled: February 13, 2004Date of Patent: September 13, 2005Assignees: Hitachi Ulsi Systems Co., Ltd., Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi