Abstract: The object of the present invention is to provide a method of manufacturing high-performance, high-breakdown-voltage semiconductor devices which suppresses an increase in the junction leakage current due to heavy metal contamination without increasing the number of manufacturing steps. A method of manufacturing semiconductor devices according to the invention, comprises the steps of ion-implanting one or more elements selected from a group of silicon, carbon, nitrogen, oxygen, hydrogen, argon, helium, and xenon into at least one surface of a semiconductor substrate of a first conductivity type at a dose of 1.times.10.sup.15 cm.sup.-2 or more to form a distortion layer, oxidizing the surface of the substrate to form an oxide film, ion-implanting impurities of a second conductivity type at a low concentration (a dose of less than 1.times.10.sup.15 cm.sup.-2) via the oxide film into the one surface of the substrate, ion-implanting impurities of the second conductivity type at a high concentration (a dose of 1.

Abstract: A channel region and a source region are formed on a surface of a substrate by double diffusion. A trench is formed so as to penetrate a part of the channel region and a part of the source region and reach the substrate. After an insulating film is formed on an inner wall of the trench, a polysilicon layer is buried up to an intermediate portion of the trench. In this state, channel ions are implanted in a side surface region of the trench, thereby depleting a channel region. Thereafter, a polysilicon layer for leading out a gate is buried in the trench.

Abstract: In a semiconductor device including a composite substrate formed by bonding first and second semiconductor substrates to each other through an oxide film and an insulator isolation trench formed from a major surface of the first semiconductor substrate to reach the oxide film and to surround an element forming region, when the potential of the second substrate is set at a potential higher than the minimum potential in the element forming region of the first substrate, an breakdown voltage can be increased. In a semiconductor integrated circuit having an element isolation region, a semiconductor device of a perfect dielectric isolation structure having an element forming region having a thickness smaller than that of the element forming region of a P-N junction isolation structure is used to reduce, e.g., a base curvature influence, thereby obtaining a further high breakdown voltage.

Abstract: A mixture of at least two types of charged particles of ions having the same value obtained by dividing the electric charge of an ion by the mass of the ion, i.e., a mixture of charged particles including hydrogen molecular ions H.sub.2.sup.+ and deuterium ions D.sup.+, is accelerated in a charged particle accelerator. Since the mass spectrograph unit in the accelerator cannot divide the hydrogen molecular ions H.sub.2.sup.+ and the deuterium ion D.sup.+, both ions are accelerated together. When the hydrogen molecular ion H.sub.2.sup.+ collides against a silicon substrate, it is divided into two hydrogen ions 2H.sup.+. Since the hydrogen ion H.sup.+ and the deuterium ion D.sup.+ have different ranges in silicon, two regions including a great number of crystal defects are formed in the silicon substrate in one ion irradiating step. As a result, at least three regions of different lifetimes of carriers are formed at different depths of the semiconductor substrate.

Abstract: In a photothyristor, a main thyristor consisting of a P emitter layer, an N base layer, a P gate base layer and an N emitter layer is formed on a semiconductor substrate. Also a pilot thyristor surrounded with the main thyristor and consisting of a P emitter layer, an N base layer, a P gate base layer and an N emitter layer is formed. In the P gate base layer, a trigger light irradiation surface including the inner surface of a recess is formed on the center of the pilot thyristor. In the N base layer, a crystal defect layer is formed under the trigger light irradiation surface by the irradiation with a radiant ray. A breakdown voltage to protect the thyristor from overvoltage is controlled by the crystal defect layer.

Abstract: A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. The gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.

Abstract: A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. THE gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.

Abstract: A dielectrically isolated structure for use in an SOI-type semiconductor device according to the present invention comprises a substrate having an element-forming region formed therein on a first insulating film, the region being made of a first material, at least one trench formed in the element-forming region and extending to the first insulating film, second insulating films formed on side walls of the trench, and a film made of a second material, and embedded in only an upper portion of the trench such that a bottom portion of the trench is hollow.

Abstract: For controlling unwanted production of crystal defects from corners of isolated regions in a complete dielectric isolation structure, after at least one trench or groove is provided through a mask of an insulating film in a semiconductor substrate adhered to an insulating film of a base substrate, the mask is side-etched and the insulating film of the base substrate is selectively etched at the same time to expose corners of the semiconductor substrate. The exposed corners of the semiconductor substrate is then subjected to isotropic etching to remove a pointed portion therefrom. Thereafter, side surfaces of the semiconductor substrate exposed within the trench is oxidized to provide an insulating film for dielectric isolation which has rounded corners.

Abstract: A semiconductor device has a semiconductor region, an electrode layer formed over the semiconductor region, and a protection layer formed to cover the semiconductor region and the electrode layer. In the semiconductor device, the protection layer is a semiconductor protection layer. Part of the semiconductive protection layer is formed thin so as to have a low resistance, permitting a corresponding portion of the electrode layer to be connected to an external bonding wire.

Abstract: A bonded substrate comprises a first semiconductor substrate in which a plurality of semiconductor elements are formed, a second semiconductor substrate adhered to the first semiconductor substrate so as to support it by means of an insulating layer interposed therebetween, a first semi-insulating polysilicon layer interposed between the first semiconductor substrate and the insulating layer, and a second semi-insulating polysilicon layer interposed between the insulating layer and the second semiconductor substrate. The semi-insulating polysilicon layers serve to reduce the voltage applied to the insulating layer and to prevent the insulating layer from being etched.