Patents by Inventor Akihiro HIKASA
Akihiro HIKASA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10468499Abstract: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.Type: GrantFiled: December 27, 2017Date of Patent: November 5, 2019Assignee: ROHM CO., LTD.Inventor: Akihiro Hikasa
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Patent number: 10411105Abstract: A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region; and a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode, a second Al-based electrode, an Al-based oxide film interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode.Type: GrantFiled: June 26, 2018Date of Patent: September 10, 2019Assignees: ROHM CO., LTD., LAPIS SEMICONDUCTOR CO., LTD.Inventors: Akihiro Hikasa, Kazusuke Kato
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Publication number: 20190172936Abstract: A semiconductor device according to the present invention includes a channel region of a first conductivity type, disposed at a front surface portion of a semiconductor layer, an emitter region of a second conductivity type, disposed at a front surface portion of the channel region, a drift region of the second conductivity type, disposed in the semiconductor layer at a rear surface side of the channel region, a collector region of the first conductivity type, disposed in the semiconductor layer at a rear surface side of the drift region, a gate trench, formed in the semiconductor layer, a gate electrode, embedded in the gate trench, and a convex region of the second conductivity type, projecting selectively from the drift region to the channel region side at a position separated from a side surface of the gate trench.Type: ApplicationFiled: February 4, 2019Publication date: June 6, 2019Inventor: Akihiro HIKASA
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Patent number: 10236368Abstract: A semiconductor device according to the present invention includes a channel region of a first conductivity type, disposed at a front surface portion of a semiconductor layer, an emitter region of a second conductivity type, disposed at a front surface portion of the channel region, a drift region of the second conductivity type, disposed in the semiconductor layer at a rear surface side of the channel region, a collector region of the first conductivity type, disposed in the semiconductor layer at a rear surface side of the drift region, a gate trench, formed in the semiconductor layer, a gate electrode, embedded in the gate trench, and a convex region of the second conductivity type, projecting selectively from the drift region to the channel region side at a position separated from a side surface of the gate trench.Type: GrantFiled: March 13, 2017Date of Patent: March 19, 2019Assignee: ROHM CO., LTD.Inventor: Akihiro Hikasa
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Publication number: 20190006497Abstract: A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is arranged in the front surface portion of the semiconductor layer, a plurality of trenches that extend from a front surface of the semiconductor layer beyond a bottom portion of the base region with an active region being defined therebetween, a plurality of first conductive-type emitter regions that are arranged in the active region, each connecting the trenches adjacent to each other, a gate electrode that is embedded in the trench, an embedding insulating film that is embedded in the trench on the gate electrode and that has an upper surface in the same height position as the front surface of the semiconductor layer or in a height position lower than the front surface and an emitter electrode that covers the active region and the embedding insulating film and that is electrically connected to the base region and the emitter region.Type: ApplicationFiled: September 10, 2018Publication date: January 3, 2019Applicant: ROHM CO., LTD.Inventor: Akihiro HIKASA
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Publication number: 20180366462Abstract: A method of manufacturing a semiconductor device includes forming a first trench and a second trench on a surface of a semiconductor substrate, the second trench being narrower than the first trench; forming an emitter connecting part and a trench gate that are separated from each other in the first trench and forming an embedded electrode in the second trench; forming a center insulating film in the first trench between the emitter connecting part and the trench gate; forming an interlayer insulating layer on the semiconductor substrate; forming a contact hole in the interlayer film at a location corresponding to the second trench; and forming an electrode material on the insulating layer so as to connect the electrode material and the embedded electrode in the second trench via the contact hole.Type: ApplicationFiled: August 28, 2018Publication date: December 20, 2018Applicant: ROHM CO., LTD.Inventor: Akihiro HIKASA
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Publication number: 20180337270Abstract: A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n+-type emitter region, a p-type base region, and an n?-type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n?-type drift region, a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other, a buried electrode filled via an insulating film in the plurality of emitter trenches, and electrically connected with the n+-type emitter region, and a p-type floating region formed between the plurality of emitter trenches, and the p-type floating region is formed deeper than the p-type base region, and includes an overlap portion that goesType: ApplicationFiled: July 31, 2018Publication date: November 22, 2018Applicant: ROHM CO., LTD.Inventor: Akihiro HIKASA
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Patent number: 10121871Abstract: A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region; and a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode, a second Al-based electrode, a barrier metal interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode.Type: GrantFiled: December 21, 2016Date of Patent: November 6, 2018Assignees: ROHM CO., LTD., LAPIS SEMICONDUCTOR CO., LTD.Inventors: Akihiro Hikasa, Kazusuke Kato
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Publication number: 20180315826Abstract: A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region; and a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode, a second Al-based electrode, an Al-based oxide film interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode.Type: ApplicationFiled: June 26, 2018Publication date: November 1, 2018Inventors: Akihiro HIKASA, Kazusuke KATO
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Patent number: 10090297Abstract: A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n+ emitter region and an n? drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the n+ emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.Type: GrantFiled: July 24, 2017Date of Patent: October 2, 2018Assignee: ROHM CO., LTD.Inventor: Akihiro Hikasa
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Patent number: 10090404Abstract: A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is arranged in the front surface portion of the semiconductor layer, a plurality of trenches that extend from a front surface of the semiconductor layer beyond a bottom portion of the base region with an active region being defined therebetween, a plurality of first conductive-type emitter regions that are arranged in the active region, each connecting the trenches adjacent to each other, a gate electrode that is embedded in the trench, an embedding insulating film that is embedded in the trench on the gate electrode and that has an upper surface in the same height position as the front surface of the semiconductor layer or in a height position lower than the front surface and an emitter electrode that covers the active region and the embedding insulating film and that is electrically connected to the base region and the emitter region.Type: GrantFiled: February 27, 2017Date of Patent: October 2, 2018Assignee: ROHM CO., LTD.Inventor: Akihiro Hikasa
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Patent number: 10062774Abstract: A semiconductor device includes a plurality of gate trenches formed in a semiconductor layer; a gate electrode filled via a gate insulating film in the plurality of gate trenches; an n+-type emitter region, a p-type base region, and an n?-type drift region disposed laterally to each gate trench; a p+-type collector region on a back surface side of the semiconductor layer; a plurality of emitter trenches formed between the gate trenches adjacent to each other; a buried electrode filled via an insulating film in the plurality of emitter trenches; and a p-type floating region formed between the plurality of emitter trenches. The p-type floating region is formed deeper than the p-type base region, and includes an overlap portion. The n+-type emitter region selectively has a pullout portion pulled out in a transverse direction along the front surface of the semiconductor layer from a side surface of the gate trench.Type: GrantFiled: December 13, 2016Date of Patent: August 28, 2018Assignee: ROHM CO., LTD.Inventor: Akihiro Hikasa
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Patent number: 10038071Abstract: A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region; and a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode, a second Al-based electrode, an Al-based oxide film interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode.Type: GrantFiled: January 19, 2017Date of Patent: July 31, 2018Assignees: ROHM CO., LTD., LAPIS SEMICONDUCTOR CO., LTD.Inventors: Akihiro Hikasa, Kazusuke Kato
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Publication number: 20180138290Abstract: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.Type: ApplicationFiled: December 27, 2017Publication date: May 17, 2018Applicant: ROHM CO., LTD.Inventor: Akihiro HIKASA
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Patent number: 9876092Abstract: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.Type: GrantFiled: May 3, 2017Date of Patent: January 23, 2018Assignee: ROHM CO., LTD.Inventor: Akihiro Hikasa
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Publication number: 20170330877Abstract: A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n+ emitter region and an n? drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the n+ emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.Type: ApplicationFiled: July 24, 2017Publication date: November 16, 2017Applicant: ROHM CO., LTD.Inventor: Akihiro HIKASA
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Publication number: 20170288026Abstract: A semiconductor device includes a semiconductor layer, having an active region, in which a functional element is formed, a first impurity region of a first conductivity type, formed at a surface layer portion of the semiconductor layer, a second impurity region of a second conductivity type, formed at a surface layer portion of the first impurity region and defining the active region, and a well region of the second conductivity type, formed along a periphery of the second impurity region at the surface layer portion of the first impurity region and having an inner side edge portion positioned at the second impurity region side, and an outer side edge portion positioned at an opposite side with respect to the second impurity region and having a second conductivity type impurity concentration lower than a second conductivity type impurity concentration of the inner side edge portion.Type: ApplicationFiled: March 30, 2017Publication date: October 5, 2017Inventor: Akihiro HIKASA
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Publication number: 20170278957Abstract: A semiconductor device according to the present invention includes a channel region of a first conductivity type, disposed at a front surface portion of a semiconductor layer, an emitter region of a second conductivity type, disposed at a front surface portion of the channel region, a drift region of the second conductivity type, disposed in the semiconductor layer at a rear surface side of the channel region, a collector region of the first conductivity type, disposed in the semiconductor layer at a rear surface side of the drift region, a gate trench, formed in the semiconductor layer, a gate electrode, embedded in the gate trench, and a convex region of the second conductivity type, projecting selectively from the drift region to the channel region side at a position separated from a side surface of the gate trench.Type: ApplicationFiled: March 13, 2017Publication date: September 28, 2017Inventor: Akihiro HIKASA
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Patent number: 9748229Abstract: A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n+ emitter region and an n? drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the n+ emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.Type: GrantFiled: November 30, 2015Date of Patent: August 29, 2017Assignee: ROHM CO., LTD.Inventor: Akihiro Hikasa
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Publication number: 20170236916Abstract: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Applicant: ROHM CO., LTD.Inventor: Akihiro HIKASA