Patents by Inventor Akihiro Yaguchi

Akihiro Yaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9964560
    Abstract: To provide a high-reliable transfer mold type sensor device in which a combined sensor including a plurality of sensors having a function of detecting physical amounts, a substrate processing a signal from the combined sensor and controlling a signal input/output with an external device, a chip pad mounted with the combined sensor and the substrate, and a lead frame are sealed with a mold resin and a package is formed, the combined sensor is configured to be thicker than the substrate and the chip pad, a principal surface side of the combined sensor is covered with the mold resin and a back surface side thereof contacts the substrate by a joint material, and the combined sensor is arranged on a package neutral surface in a cross-section of a thickness direction of the package including the combined sensor, the substrate, and the chip pad.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: May 8, 2018
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Akihiro Yaguchi, Masahide Hayashi, Kazunori Ohta, Akihiro Okamoto
  • Publication number: 20160146849
    Abstract: To provide a resin-sealed sensor device in which a sensor element that detects an inertial force such as acceleration or angular velocity is mounted on a pad, and the entire thereof is molded by resin, the resin-sealed sensor device with a high reliability by suppressing or resolving a sensor output error by reducing or resolving inclination or deformation of the sensor element or the pad at the time of resin injection, in a resin-sealed sensor device 100 including: a circuit unit 10 that includes a sensor element 1 for detection of a physical quantity, a semiconductor chip 2, a pad 3 of which shape in a plan view has any shape among a rectangle, a circle and an ellipse, and supported leads 5A to 5D and an outer conductor lead 4 to be connected to the pad 3; and a molded resin body 20 that seals the circuit unit 10, each of the supported leads 5A to 5D is arranged in each divided regions to be formed by dividing the shape into four virtual regions when an intersection point O between two axes L1 and L2, perpe
    Type: Application
    Filed: February 5, 2014
    Publication date: May 26, 2016
    Inventors: Akihiro YAGUCHI, Masahide HAYASHI
  • Publication number: 20160131678
    Abstract: To provide a high-reliable transfer mold type sensor device in which a combined sensor including a plurality of sensors having a function of detecting physical amounts, a substrate processing a signal from the combined sensor and controlling a signal input/output with an external device, a chip pad mounted with the combined sensor and the substrate, and a lead frame are sealed with a mold resin and a package is formed, the combined sensor is configured to be thicker than the substrate and the chip pad, a principal surface side of the combined sensor is covered with the mold resin and a back surface side thereof contacts the substrate by a joint material, and the combined sensor is arranged on a package neutral surface in a cross-section of a thickness direction of the package including the combined sensor, the substrate, and the chip pad.
    Type: Application
    Filed: February 5, 2014
    Publication date: May 12, 2016
    Inventors: Akihiro YAGUCHI, Masahide HAYASHI, Kazunori OHTA, Akihiro OKAMOTO
  • Patent number: 8878062
    Abstract: A cable connection structure includes a multi-core coaxial cable connected to a board. The multi-core coaxial cable includes a plurality of parallel-arranged coaxial cables each including a center conductor and an inner insulator, an outer conductor and an outer insulator sequentially formed on an outer periphery of the center conductor. The board includes a signal electrode connected to the center conductor and a ground electrode connected to the outer conductor. The cable connection structure further includes a positioning member lying between the signal electrode and the ground electrode for positioning the center conductor while the inner insulator is attached to the positioning member.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: November 4, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventors: Kotaro Tanaka, Akihiro Yaguchi, Hiroshi Oyama
  • Patent number: 8308503
    Abstract: A flat cable includes a plurality of conductors arranged in parallel and exposed at both end portions in a longitudinal direction thereof, an insulation film covering the plurality of conductors except the exposed both end portions, and a reinforcing member that covers the plurality of conductors along a width direction of the plurality of conductors, is provided on a surface of the insulation film in a part of a region including an edge of the insulation film, and includes a metal plate and an insulative covering layer for covering the metal plate.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: November 13, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Akihiro Yaguchi, Takumi Kobayashi, Kenichi Murakami, Hiroaki Komatsu
  • Publication number: 20120276772
    Abstract: A flat cable includes a plurality of conductors arranged in parallel, an insulating member covering the plurality of conductors, a first reinforcing member on a surface of an end portion of the insulating member, and a second reinforcing member on an opposite side of the first reinforcing member across the conductor and the insulating member. The first reinforcing member includes a reinforcing metal plate including an end portion bent toward the second reinforcing member, a covering member covering at least a portion of a periphery of the reinforcing metal plate, and an adhesive interposed between the reinforcing metal plate and the covering member and between the covering member and the insulating member to bond the reinforcing metal plate to the covering member and the covering member to the insulating member. The second reinforcing member has a rigidity greater than that of the covering member of the first reinforcing member.
    Type: Application
    Filed: August 5, 2011
    Publication date: November 1, 2012
    Applicant: Hitachi Cable, Ltd.
    Inventors: Akihiro Yaguchi, Takumi Kobayashi, Kenichi Murakami, Hiroaki Komatsu
  • Patent number: 8282412
    Abstract: A flat cable includes a plurality of conductors arranged in parallel, an insulating member covering the plurality of conductors, a first reinforcing member on a surface of an end portion of the insulating member, and a second reinforcing member on an opposite side of the first reinforcing member across the conductor and the insulating member. The first reinforcing member includes a reinforcing metal plate including an end portion bent toward the second reinforcing member, a covering member covering at least a portion of a periphery of the reinforcing metal plate, and an adhesive interposed between the reinforcing metal plate and the covering member and between the covering member and the insulating member to bond the reinforcing metal plate to the covering member and the covering member to the insulating member. The second reinforcing member has a rigidity greater than that of the covering member of the first reinforcing member.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 9, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Akihiro Yaguchi, Takumi Kobayashi, Kenichi Murakami, Hiroaki Komatsu
  • Publication number: 20120184130
    Abstract: A flat cable includes a plurality of conductors arranged in parallel and exposed at both end portions in a longitudinal direction thereof, an insulation film covering the plurality of conductors except the exposed both end portions, and a reinforcing member that covers the plurality of conductors along a width direction of the plurality of conductors, is provided on a surface of the insulation film in a part of a region including an edge of the insulation film, and includes a metal plate and an insulative covering layer for covering the metal plate.
    Type: Application
    Filed: August 5, 2011
    Publication date: July 19, 2012
    Applicant: Hitachi Cable, Ltd.
    Inventors: Akihiro Yaguchi, Takumi Kobayashi, Kenichi Murakami, Hiroaki Komatsu
  • Publication number: 20110306235
    Abstract: A cable connection structure includes a multi-core coaxial cable connected to a board. The multi-core coaxial cable includes a plurality of parallel-arranged coaxial cables each including a center conductor and an inner insulator, an outer conductor and an outer insulator sequentially formed on an outer periphery of the center conductor. The board includes a signal electrode connected to the center conductor and a ground electrode connected to the outer conductor. The cable connection structure further includes a positioning member lying between the signal electrode and the ground electrode for positioning the center conductor while the inner insulator is attached to the positioning member.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 15, 2011
    Applicant: Hitachi Cable, Ltd.
    Inventors: Kotaro Tanaka, Akihiro Yaguchi, Hiroshi Oyama
  • Patent number: 7572674
    Abstract: In a production of a semiconductor device, after a step in which a thermosetting resin is thermally cured to seal a semiconductor chip with the resin and before a step in which a characteristic of the semiconductor chip is inspected, the thermosetting resin is baked at a temperature higher than the resin sealing temperature in said resin sealing step.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: August 11, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kouta Nagano, Hideo Miura, Akihiro Yaguchi
  • Patent number: 7388295
    Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The distance between farthest ones of external terminal positioned at an outermost end portions of said second semiconductor chip is smaller than that of the first semiconductor chip.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: June 17, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Atsushi Kazama, Akihiro Yaguchi, Hideo Miura, Asao Nishimura
  • Publication number: 20060125116
    Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The distance between farthest ones of external terminal positioned at an outermost end portions of said second semiconductor chip is smaller than that of the first semiconductor chip.
    Type: Application
    Filed: February 10, 2006
    Publication date: June 15, 2006
    Inventors: Atsushi Kazama, Akihiro Yaguchi, Hideo Miura, Asao Nishimura
  • Patent number: 7038322
    Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: May 2, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kazama, Akihiro Yaguchi, Hideo Miura, Asao Nishimura
  • Publication number: 20050227384
    Abstract: In a production of a semiconductor device, after a step in which a thermosetting resin is thermally cured to seal a semiconductor chip with the resin and before a step in which a characteristic of the semiconductor chip is inspected, the thermosetting resin is baked at a temperature higher than the resin sealing temperature in said resin sealing step.
    Type: Application
    Filed: September 26, 2002
    Publication date: October 13, 2005
    Inventors: Kouta Nagano, Hideo Miura, Akihiro Yaguchi
  • Patent number: 6927489
    Abstract: In a small semiconductor device having external terminals on a semiconductor element and a semiconductor module mounted with the small semiconductor device, disconnection of the external terminals is prevented when a temperature change occurs under the conditions that the semiconductor device is mounted on a printed circuit board. To achieve this a projection is formed on a land which is an external terminal bonding area of the semiconductor device, and a protruded portion of the projection is bonded to the external terminal. An intervening portion of a protective film made of resin material is formed between the lands and semiconductor element.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: August 9, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Akihiro Yaguchi, Hideo Miura, Atsushi Kazama, Asao Nishimura
  • Patent number: 6919622
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: July 19, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Publication number: 20050029674
    Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.
    Type: Application
    Filed: August 17, 2004
    Publication date: February 10, 2005
    Inventors: Atsushi Kazama, Akihiro Yaguchi, Hideo Miura, Asao Nishimura
  • Patent number: 6844219
    Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: January 18, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Makoto Kitano, Akihiro Yaguchi, Naotaka Tanaka, Takeshi Terasaki, Ichiro Anjoh, Ryo Haruta, Asao Nishimura, Junichi Saeki
  • Patent number: 6777816
    Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: August 17, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kazama, Akihiro Yaguchi, Hideo Miura, Asao Nishimura
  • Publication number: 20040155323
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Application
    Filed: February 10, 2004
    Publication date: August 12, 2004
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto