Patents by Inventor Akihisa Uchida

Akihisa Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10895043
    Abstract: A track includes a travel path including a travel face with which travel wheels of a vehicle come into contact while rolling. The travel path includes a plurality of travel path forming units that are arranged to be adjacent to each other in a travel direction of the vehicle and of which each includes a unit travel face forming part of the travel face and a positioning unit that fixes a relative position between travel path forming units adjacent to each other.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: January 19, 2021
    Assignee: MITSUBISHI HEAVY INDUSTRIES ENGINEERING, LTD.
    Inventors: Toshiaki Asanoma, Yukihide Yanobu, Hiroyuki Kono, Koji Uchida, Akihisa Kawauchi, Yoshinobu Murakami, Yasuyuki Mukai
  • Publication number: 20200148237
    Abstract: This abnormality monitoring device is equipped with: an acceleration data acquisition unit for acquiring measurement data about the acceleration of a vehicle chassis; an abnormality presence determination unit for determining whether an abnormality is present on the basis of a comparison between the acceleration and a threshold; a frequency analysis unit for analyzing the acceleration frequency when the abnormality presence determination unit determines that an abnormality is present, and an abnormality type identification unit for identifying abnormality type on the basis of the frequency pattern.
    Type: Application
    Filed: February 16, 2018
    Publication date: May 14, 2020
    Inventors: Akihisa KAWAUCHI, Hiroyuki KONO, Koji UCHIDA, Katsuya KUROKI, So TAMURA
  • Publication number: 20190276043
    Abstract: A steering control system includes: a deviation amount detection unit configured to detect a deviation amount of a car that travels on a track, from a reference traveling path of the car in a width direction of the track; a roll or lateral direction vibration amount detection unit configured to detect a roll or lateral direction vibration amount of the car; and a feedback control unit configured to perform feedback control of steering of the car so as to reduce the deviation amount and the roll or lateral direction vibration amount. The feedback control unit is configured to output a steering command value in which a specified frequency to be reduced is suppressed.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 12, 2019
    Inventors: Koji UCHIDA, Hiroyuki KONO, Akihisa KAWAUCHI
  • Patent number: 9503018
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: November 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Publication number: 20160142011
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 19, 2016
    Inventors: Toshiaki TSUTSUMI, Yoshihiro FUNATO, Tomonori OKUDAIRA, Tadato YAMAGATA, Akihisa UCHIDA, Takeshi TERASAKI, Tomohisa SUZUKI, Yoshiharu KANEGAE
  • Patent number: 9252793
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: February 2, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Publication number: 20130314165
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Application
    Filed: November 29, 2010
    Publication date: November 28, 2013
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Publication number: 20080258177
    Abstract: Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.
    Type: Application
    Filed: April 14, 2008
    Publication date: October 23, 2008
    Inventors: Hiroyuki IKEDA, Toshio Sasaki, Akinobu Watanabe, Toshio Yamada, Akihisa Uchida
  • Publication number: 20060214721
    Abstract: Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.
    Type: Application
    Filed: May 17, 2006
    Publication date: September 28, 2006
    Inventors: Hiroyuki Ikeda, Toshio Sasaki, Akinobu Watanabe, Toshio Yamada, Akihisa Uchida
  • Patent number: 7073147
    Abstract: Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: July 4, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hiroyuki Ikeda, Toshio Sasaki, Akinobu Watanabe, Toshio Yamada, Akihisa Uchida
  • Publication number: 20040157378
    Abstract: Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.
    Type: Application
    Filed: October 29, 2003
    Publication date: August 12, 2004
    Inventors: Hiroyuki Ikeda, Toshio Sasaki, Akinobu Watanabe, Toshio Yamada, Akihisa Uchida
  • Patent number: 5388073
    Abstract: A semiconductor memory device for use in a digital data processor together with a central processing unit (CPU) receives address signals which are validated for a time period n times as long as the machine cycle of the CPU, and it stores therein input data items which are validated for a cycle equal to the machine cycle of the CPU or delivers therefrom output data items which are validated for a cycle equal to the machine cycle of the CPU.
    Type: Grant
    Filed: April 15, 1991
    Date of Patent: February 7, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Masami Usami, Akihisa Uchida, Yoshino Sakai, Masato Iwabuchi
  • Patent number: 5351211
    Abstract: An integrated circuit including latch circuits disposed on the input and output sides of an object circuit the delay time of which is to be measured, respectively, and a variable delay circuit capable of arbitrarily delaying a timing signal supplied from outside or a timing signal generated inside the integrated circuit by an instruction from outside. The timing signal and a delay signal obtained by delaying the input signal by the variable delay circuit are supplied as clock signals to the latch circuits, and the signal passing through the variable delay circuit is fed back to the input side so as to constitute an oscillation circuit, the oscillation signal of which can be outputted to outside. A signal delayed by a desired time can be automatically generated inside the semiconductor integrated circuit on the basis of this timing signal.
    Type: Grant
    Filed: July 23, 1993
    Date of Patent: September 27, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Keiichi Higeta, Sohei Omori, Yasuhiro Fujimura, Etsuko Iwamoto, Akihisa Uchida
  • Patent number: 5214302
    Abstract: A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region.
    Type: Grant
    Filed: December 13, 1991
    Date of Patent: May 25, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Uchida, Keiichi Higeta, Nobuo Tamba, Masanori Odaka, Katsumi Ogiue
  • Patent number: 5200348
    Abstract: A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body.The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.
    Type: Grant
    Filed: December 3, 1991
    Date of Patent: April 6, 1993
    Assignee: Hatachi, Ltd.
    Inventors: Akihisa Uchida, Daisuke Okada, Toshihiko Takakura, Katsumi Ogiue, Yoichi Tamaki, Masao Kawamura
  • Patent number: 5177584
    Abstract: A bipolar SRAM which includes a forward bipolar transistor and a reverse bipolar transistor on an identical semiconductor substrate, is disclosed. Concretely, the base region of the reverse bipolar transistor is formed at a deeper position of the substrate than the base region of the forward bipolar transistor, thereby to heighten the cutoff frequency f.sub.T of the reverse bipolar transistor.
    Type: Grant
    Filed: January 28, 1991
    Date of Patent: January 5, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Uchida, Yuji Yatsuda, Katsumi Ogiue, Kazuo Nakazato, Takahiro Onai
  • Patent number: 5141888
    Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease.
    Type: Grant
    Filed: January 18, 1991
    Date of Patent: August 25, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Mikinori Kawaji, Toshihiko Takakura, Akihisa Uchida, Shigeo Kuroda, Yoichi Tamaki, Takeo Shiba, Kazuhiko Sagara, Masao Kawamura
  • Patent number: 5128740
    Abstract: This invention relates to a semiconductor integrated circuit device including highly self-aligned bipolar transistors. The semiconductor integrated circuit device a semiconductor body at least a first protruding portion and a hollow portion, disposed as a trench. The hollow portion being adjacent to the first protruding portion and being lower than an upper surface of the first protruding portion and including an isolation groove which is formed along a side surface of the protruding portion and in self-alignment with a peripheral edge portion of the upper surface of the first protruding portion.
    Type: Grant
    Filed: November 17, 1989
    Date of Patent: July 7, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Uchida, Katsumi Ogiue, Toru Koizumi, Keiichi Higeta
  • Patent number: 5084402
    Abstract: A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body.The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.
    Type: Grant
    Filed: May 17, 1989
    Date of Patent: January 28, 1992
    Assignee: Hitachi, Ind.
    Inventors: Akihisa Uchida, Daisuke Okaka, Toshihiko Takakura, Katsumi Ogiue, Yoichi Tamaki, Masao Kawamura
  • Patent number: 5029127
    Abstract: There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a common signal therethrough such as with respect to the individual word lines. The word lines implemented are formed from at least a pair of stacked conductive layers and which layers have interposed therebetween an insulating film. The pair of layers form a pair of wiring lines wherein together they form a work line and wherein the wiring lines are, furthermore, interconnected at predetermined intervals along the lengths thereof. This leads to the ability to decrease the chip size of semiconductor integrated circuits noting that a decrease in the voltage drop of a signal line results, and to prevent electromigration in the signal (wiring) lines.
    Type: Grant
    Filed: May 15, 1990
    Date of Patent: July 2, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Uchida, Ichiro Mitamura, Keiichi Higeta