Patents by Inventor Akihisa Uchida

Akihisa Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5029127
    Abstract: There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a common signal therethrough such as with respect to the individual word lines. The word lines implemented are formed from at least a pair of stacked conductive layers and which layers have interposed therebetween an insulating film. The pair of layers form a pair of wiring lines wherein together they form a work line and wherein the wiring lines are, furthermore, interconnected at predetermined intervals along the lengths thereof. This leads to the ability to decrease the chip size of semiconductor integrated circuits noting that a decrease in the voltage drop of a signal line results, and to prevent electromigration in the signal (wiring) lines.
    Type: Grant
    Filed: May 15, 1990
    Date of Patent: July 2, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Uchida, Ichiro Mitamura, Keiichi Higeta
  • Patent number: 5011788
    Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease.
    Type: Grant
    Filed: December 15, 1988
    Date of Patent: April 30, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Mikinori Kawaji, Toshihiko Takakura, Akihisa Uchida, Shigeo Kuroda, Yoichi Tamaki, Takeo Shiba, Kazuhiko Sagara, Masao Kawamura
  • Patent number: 4949162
    Abstract: A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).
    Type: Grant
    Filed: June 3, 1988
    Date of Patent: August 14, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Kiyoji Ikeda, Toru Nakamura, Akihisa Uchida, Toru Koizumi, Hiromichi Enami, Satoru Isomura, Shinji Nakajima, Katsumi Ogiue, Kaoru Ohgaya
  • Patent number: 4926378
    Abstract: There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a common signal therethrough such as with respect to the individual word lines. The word lines implemented are formed from at least a pair of stacked conductive layers of a material whose principal component is aluminum and which layers have interposed therebetween an insulating film. The pair of layers form a pair of wiring lines corresponding together to a word line and wherein the wiring lines are, furthermore, interconnected at predetermined intervals along the lengths thereof. This leads to the ability to decrease the chip size of semiconductor integrated circuits noting that a decrease in the voltage drop of a signal line results, and to prevent electromigration in the signal (wiring) lines.
    Type: Grant
    Filed: February 25, 1988
    Date of Patent: May 15, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Uchida, Ichiro Mitamura, Keiichi Higeta
  • Patent number: 4926235
    Abstract: A semiconductor device is disclosed, which includes bipolar transistor each having an emitter, base and collector formed inside each protruding portion of a semiconductor substrate, and trenches for device isolation. The bipolar transistor and the trench are spaced apart from each other by a predetermined spacing. According to this arrangement, the width of a base contact becomes uniform and any change of transistor characteristics can be prevented effectively.
    Type: Grant
    Filed: October 13, 1987
    Date of Patent: May 15, 1990
    Inventors: Yoichi Tamaki, Tokuo Kure, Tohru Nakamura, Tetsuya Hayashida, Kiyoji Ikeda, Katsuyoshi Washio, Takahiro Onai, Akihisa Uchida, Kunihiko Watanabe
  • Patent number: 4907063
    Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.
    Type: Grant
    Filed: May 20, 1987
    Date of Patent: March 6, 1990
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Daisuke Okada, Akihisa Uchida, Toshihiko Takakura, Shinji Nakashima, Nobuhiko Ohno, Katsumi Ogiue
  • Patent number: 4853343
    Abstract: A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body.The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.
    Type: Grant
    Filed: March 18, 1988
    Date of Patent: August 1, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Uchida, Daisuke Okada, Toshihiko Takakura, Katsumi Ogiue, Yoichi Tamaki, Masao Kawamura
  • Patent number: 4819054
    Abstract: A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease.
    Type: Grant
    Filed: February 6, 1987
    Date of Patent: April 4, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Mikinori Kawaji, Toshihiko Takakura, Akihisa Uchida, Shigeo Kuroda, Yoichi Tamaki, Takeo Shiba, Kazuhiko Sagara, Masao Kawamura
  • Patent number: 4809052
    Abstract: A semiconductor memory device is provided such as the type having flip-flop memory cells each including two bipolar transistors in cross connection with each other. In certain embodiments, at least a part of a Schottky barrier diode or capacitor in the memory cell is formed under a digit line. This memory device is greatly reduced in its required area, and the Schottky barrier diode and capacitor are negligibly influenced by the digit line. In other embodiments, it is arranged to provide different electrodes for the Schottky barrier diode and the capacitor to optimize construction in a minimized space.
    Type: Grant
    Filed: May 7, 1986
    Date of Patent: February 28, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Yasushiro Nishioka, Takeo Shiba, Hiroshi Shinriki, Kiichiro Mukai, Akihisa Uchida, Ichiro Mitamura, Keiichi Higeta, Katsumi Ogiue, Kunihiko Yamaguchi, Noriyuki Sakuma
  • Patent number: 4746963
    Abstract: A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body. The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.
    Type: Grant
    Filed: December 29, 1986
    Date of Patent: May 24, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Uchida, Daisuke Okada, Toshihiko Takakura, Katsumi Ogiue, Yoichi Tamaki, Masao Kawamura
  • Patent number: 4700464
    Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.
    Type: Grant
    Filed: October 15, 1984
    Date of Patent: October 20, 1987
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Daisuke Okada, Akihisa Uchida, Toshihiko Takakura, Shinji Nakashima, Nobuhiko Ohno, Katsumi Ogiue