Abstract: A phase detector includes: a phase shift circuit to phase-shift a first positive-phase signal included in a first differential signal and a first negative-phase signal included in the first differential signal, and phase-shift a second positive-phase signal included in a second differential signal and a second negative-phase signal included in the second differential signal; a multiplication circuit to perform multiplication of two signals for all combinations of the first positive-phase signal and the first negative-phase signal with the phase-shifted second positive-phase signal and the phase-shifted second negative-phase signal, and perform multiplication of two signals for all combinations of the phase-shifted first positive-phase signal and the phase-shifted first negative-phase signal with the second positive-phase signal and the second negative-phase signal; and a phase difference calculating circuit to calculate a phase difference between the first differential signal and the second differential signa

Abstract: A third signal having a phase intermediate between a first signal based on a reference signal and a second signal with a phase shifted by an element of a previous stage is generated, a signal obtained by shifting the phase of the third signal by a first phase shill amount is output as a second signal to an element of a subsequent stage, a phase difference between the third signal and a fourth signal obtained by shifting the phase of a first signal output from the element of the subsequent stage by the first phase shift amount is detected, and the first phase shift amount is controlled on the basis of the detected phase difference.

Abstract: An antenna device includes: a patch conductor provided on a substrate; a GND conductor provided in the substrate in such a manner as to face the patch conductor; GND pins that are provided in the substrate and that connect the patch conductor and the GND conductor; and an RF circuit provided on a first face of the patch conductor opposite to a second face of the patch conductor, the second face being attached to the substrate, the RF circuit being provided in such a manner as to be surrounded by the GND pins.

Abstract: There is provided an active phased array antenna in which power to an Si wafer is separated from power to compound semiconductor chips. An active phased array antenna is an active phased array antenna including a substrate having a plurality of antenna elements; a pseudo wafer containing a group of semiconductor chips including a plurality of semiconductor chips made of compound semiconductors; and a silicon wafer made of silicon, the substrate, the pseudo wafer, and the silicon wafer being stacked on top of each other in this order, and the pseudo wafer includes first feeders for supplying power to the group of semiconductor chips from the substrate; and a second feeder for supplying power to the silicon wafer from the substrate, the second feeder passing through the pseudo wafer in a thickness direction of the pseudo wafer.

Abstract: A mixer includes a first unit mixer, a second unit mixer, a third unit mixer, and a fourth unit mixer that have the same configuration and a first combiner, a second combiner, and a third combiner that have the same configuration. The first to the fourth unit mixers each include a differential RF signal terminal. Output of the first unit mixer and output of the second unit mixer are combined by the second combiner. Output of the third unit mixer and output of the fourth unit mixer are combined by the third combiner. Output of the second combiner and output of the third combiner are combined by the first combiner. The output of the third unit mixer is input to the third combiner with the polarity being determined.

Abstract: An image rejection mixer includes a delay circuit for delaying one of first signals divided by a distribution circuit and a second signal provided to a second mixing circuit by the same delay amount d, or delaying the other one of the first signals divided by the distribution circuit and the second signal provided to a first mixing circuit by the same delay amount d.

Abstract: A phase detector includes: a phase shift circuit to phase-shift a first positive-phase signal included in a first differential signal and a first negative-phase signal included in the first differential signal, and phase-shift a second positive-phase signal included in a second differential signal and a second negative-phase signal included in the second differential signal; a multiplication circuit to perform multiplication of two signals for all combinations of the first positive-phase signal and the first negative-phase signal with the phase-shifted second positive-phase signal and the phase-shifted second negative-phase signal, and perform multiplication of two signals for all combinations of the phase-shifted first positive-phase signal and the phase-shifted first negative-phase signal with the second positive-phase signal and the second negative-phase signal; and a phase difference calculating circuit to calculate a phase difference between the first differential signal and the second differential signa

Abstract: A dielectric heating device is provided with two or more electrodes, a grounded surface connected to a first electrode, a signal source connected to a second electrode to output a high-frequency signal, a first element interposed serially between the signal source and second electrode, and a second element interposed serially between the grounded surface and first electrode. The first element includes two terminals that electrically connect the signal source and second electrode in a non-contact manner, to cause the high-frequency signal outputted from the signal source to pass through the first element, by using the electric coupling between the two terminals. The second element includes two terminals that electrically connect the grounded surface and first electrode in a non-contact manner, to output, by using the electric coupling between the two terminals, the high-frequency signal outputted from the signal source, to the grounded surface.

Abstract: A third signal having a phase intermediate between a first signal based on a reference signal and a second signal with a phase shifted by an element of a previous stage is generated, a signal obtained by shifting the phase of the third signal by a first phase shill amount is output as a second signal to an element of a subsequent stage, a phase difference between the third signal and a fourth signal obtained by shifting the phase of a first signal output from the element of the subsequent stage by the first phase shift amount is detected, and the first phase shift amount is controlled on the basis of the detected phase difference.

Abstract: A mixer includes: a VGA (12) configured to amplify one of divided two portions of an input signal at a gain of cos ?; a VGA (13) configured to amplify another one of the divided two portions of the input signal at a gain of sin ?; an IQ generator (15) configured to input an LO wave, and output an LO wave in phase with the input LO wave and an LO wave having a phase difference of 90° with respect to the input LO wave; a mixer (16) configured to input the signal output from the VGA (12) and the LO wave which is output from the IQ generator (15), to output an RF signal; a second mixer (17) configured to input the signal from the VGA (13) and the LO wave which is output from the IQ generator, to output an RF signal; and a combiner (18).

Abstract: A mixer includes a first unit mixer, a second unit mixer, a third unit mixer, and a fourth unit mixer that have the same configuration and a first combiner, a second combiner, and a third combiner that have the same configuration. The first to the fourth unit mixers each include a differential RF signal terminal. Output of the first unit mixer and output of the second unit mixer are combined by the second combiner. Output of the third unit mixer and output of the fourth unit mixer are combined by the third combiner. Output of the second combiner and output of the third combiner are combined by the first combiner. The output of the third unit mixer is input to the third combiner with the polarity being determined.

Abstract: A phase-locked loop circuit includes: a division ratio control circuit controlling a division ratio of an output signal of a variable frequency divider on the basis of an addition signal of a negative feedback signal and a division ratio setting signal indicating the division ratio, in synchronization with a divided signal output from the variable frequency divider; a first phase detection circuit calculating a first phase detection signal indicating a phase of an output signal of a signal output circuit; a second phase detection circuit calculating a second phase detection signal indicating a phase of the output signal of a case where it is assumed that the division ratio control circuit controls the division ratio of the output signal of the variable frequency divider in synchronization with the reference signal; and a shift circuit generating a negative feedback signal from a difference between the first phase detection signal and the second phase detection signal, and outputting an addition signal of the

Abstract: An IQ signal source (100) includes: a Q-VCO (3) having a first VCO (1) and a second VCO (2), the IQ signal source (100) outputting an I signal and a Q signal by electrically coupling the first VCO (1) and the second VCO (2) with each other; a first PLL (10) for comparing a frequency of the I signal or the Q signal with a frequency of a reference signal input from the outside of the IQ signal source (100) and outputting a voltage depending on a result of the comparison; and a second PLL (9) for detecting an IQ phase difference and outputting a voltage depending on the IQ phase difference. The IQ phase difference converges to 90 degrees in dependence on the output voltage of the first PLL (10) and the output voltage of the second PLL (9).

Abstract: An IQ signal source (100) includes: a Q-VCO (3) having a first VCO (1) and a second VCO (2), the IQ signal source (100) outputting an I signal and a Q signal by electrically coupling the first VCO (1) and the second VCO (2) with each other; a first PLL (10) for comparing a frequency of the I signal or the Q signal with a frequency of a reference signal input from the outside of the IQ signal source (100) and outputting a voltage depending on a result of the comparison; and a second PLL (9) for detecting an IQ phase difference and outputting a voltage depending on the IQ phase difference. The IQ phase difference converges to 90 degrees in dependence on the output voltage of the first PLL (10) and the output voltage of the second PLL (9).

Abstract: There has been a problem that linearity is degraded in the conventional amplifier when the idle current is reduced in order to lower the power consumption. An amplifier of the present invention includes: a bias circuit to cause a bias current to flow; an amplifying element to amplify a signal by causing an output current corresponding to the bias current to flow; a bias current subtracting circuit to detect the signal and subtract, from the bias current, a current based on an amplitude of the signal detected; and a bias current adding circuit having an operation starting point higher than an operation starting point of the bias current subtracting circuit, and to detect the signal and add, to the bias current, a current based on an amplitude of the signal detected.

Abstract: A phase-locked loop circuit includes: a division ratio control circuit controlling a division ratio of an output signal of a variable frequency divider on the basis of an addition signal of a negative feedback signal and a division ratio setting signal indicating the division ratio, in synchronization with a divided signal output from the variable frequency divider; a first phase detection circuit calculating a first phase detection signal indicating a phase of an output signal of a signal output circuit; a second phase detection circuit calculating a second phase detection signal indicating a phase of the output signal of a case where it is assumed that the division ratio control circuit controls the division ratio of the output signal of the variable frequency divider in synchronization with the reference signal; and a shift circuit generating a negative feedback signal from a difference between the first phase detection signal and the second phase detection signal, and outputting an addition signal of the

Abstract: A local oscillator of the present invention includes: a frequency generator for outputting first and second sinusoidal signals having the same frequency but mutually different phases; a phase detector for outputting either a positive or a negative voltage depending on whether a phase difference between the first and second sinusoidal signals output from the frequency generator is greater than a reference phase difference; and a comparator for outputting a comparison result between a voltage output from the phase detector and a reference voltage, or a comparison result between the voltage output from the phase detector and a voltage obtained by inverting the polarity of the voltage, in which the frequency generator controls the phase of the first sinusoidal signal so that the phase difference approaches the reference phase difference by using the comparison result output from the comparator, enabling generating IQ signals having higher phase accuracy than conventional local oscillators.

Abstract: A local oscillator of the present invention includes: a frequency generator for outputting first and second sinusoidal signals having the same frequency but mutually different phases; a phase detector for outputting either a positive or a negative voltage depending on whether a phase difference between the first and second sinusoidal signals output from the frequency generator is greater than a reference phase difference; and a comparator for outputting a comparison result between a voltage output from the phase detector and a reference voltage, or a comparison result between the voltage output from the phase detector and a voltage obtained by inverting the polarity of the voltage, in which the frequency generator controls the phase of the first sinusoidal signal so that the phase difference approaches the reference phase difference by using the comparison result output from the comparator, enabling generating IQ signals having higher phase accuracy than conventional local oscillators.

Abstract: What is provided are: two or more electrodes; a grounded surface connected to a first one of the electrodes; a signal source that is connected to a second one of the electrodes, and that outputs a high-frequency signal; a high-frequency passing heat-insulation element that is interposed serially between the signal source and the second electrode, that includes two terminals which are electrically coupled mutually and without contact with each other to electrically connect the signal source and the second electrode in a non-contact manner, and that causes the high-frequency signal outputted from the signal source to pass therethrough, by using the electric coupling between the two terminals; and a high-frequency passing heat-insulation element that is interposed serially between the grounded surface and the first electrode, that includes two terminals which are electrically coupled mutually and without contact with each other to electrically connect the grounded surface and the first electrode in a non-contact

Abstract: An image rejection mixer includes a delay circuit for delaying one of first signals divided by a distribution circuit and a second signal provided to a second mixing circuit by the same delay amount d, or delaying the other one of the first signals divided by the distribution circuit and the second signal provided to a first mixing circuit by the same delay amount d.