Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an

Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an

Abstract: A mixer includes: a VGA (12) configured to amplify one of divided two portions of an input signal at a gain of cos ?; a VGA (13) configured to amplify another one of the divided two portions of the input signal at a gain of sin ?; an IQ generator (15) configured to input an LO wave, and output an LO wave in phase with the input LO wave and an LO wave having a phase difference of 90° with respect to the input LO wave; a mixer (16) configured to input the signal output from the VGA (12) and the LO wave which is output from the IQ generator (15) , to output an RF signal; a second mixer (17) configured to input the signal from the VGA (13) and the LO wave which is output from the IQ generator, to output an RF signal; and a combiner (18).

Abstract: A first transistor (2a), a second transistor (2b), a third transistor (2c) and a fourth transistor (2d) are provided. A first transistor (2a) amplifies a first I signal VIP inputted from a first input terminal (1a). A second transistor (2b) amplifies a first Q signal VQP inputted from a second input terminal (1b). A third transistor (2c) amplifies a second I signal VIN when the second I signal VIN is inputted from a third input terminal (1c), the second I signal VIN forming a differential signal with the first I signal VIP. A fourth transistor (2d) amplifies a second Q signal VQN when the second Q signal VQN is inputted from a fourth input terminal (1d), the second Q signal VQN forming a differential signal with the first Q signal VQP.

Abstract: A local oscillator of the present invention includes: a frequency generator for outputting first and second sinusoidal signals having the same frequency but mutually different phases; a phase detector for outputting either a positive or a negative voltage depending on whether a phase difference between the first and second sinusoidal signals output from the frequency generator is greater than a reference phase difference; and a comparator for outputting a comparison result between a voltage output from the phase detector and a reference voltage, or a comparison result between the voltage output from the phase detector and a voltage obtained by inverting the polarity of the voltage, in which the frequency generator controls the phase of the first sinusoidal signal so that the phase difference approaches the reference phase difference by using the comparison result output from the comparator, enabling generating IQ signals having higher phase accuracy than conventional local oscillators.

Abstract: There has been a problem that linearity is degraded in the conventional amplifier when the idle current is reduced in order to lower the power consumption. An amplifier of the present invention includes: a bias circuit to cause a bias current to flow; an amplifying element to amplify a signal by causing an output current corresponding to the bias current to flow; a bias current subtracting circuit to detect the signal and subtract, from the bias current, a current based on an amplitude of the signal detected; and a bias current adding circuit having an operation starting point higher than an operation starting point of the bias current subtracting circuit, and to detect the signal and add, to the bias current, a current based on an amplitude of the signal detected.

Abstract: A first transistor (2a), a second transistor (2b), a third transistor (2c) and a fourth transistor (2d) are provided. A first transistor (2a) amplifies a first I signal VIP inputted from a first input terminal (1a). A second transistor (2b) amplifies a first Q signal VQP inputted from a second input terminal (1b). A third transistor (2c) amplifies a second I signal VIN when the second I signal VIN is inputted from a third input terminal (1c), the second I signal VIN forming a differential signal with the first I signal VIP. A fourth transistor (2d) amplifies a second Q signal VQN when the second Q signal VQN is inputted from a fourth input terminal (1d), the second Q signal VQN forming a differential signal with the first Q signal VQP.

Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an

Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an

Abstract: Besides a time constant circuit 5 that imposes a frequency limit on a wireless signal detected by a power detecting circuit 4 at a preset time constant Ta, there is provided a time constant circuit 8 that imposes a frequency limit on the wireless signal at a time constant Tb greater than the time constant Ta. When the signal level of an intermittent operation signal supplied from a signal input terminal 1 is H level or when a threshold processing circuit 6 decides that the level of the wireless signal is higher than a threshold Th, a logic unit 3 supplies a control signal that instructs starting to the power detecting circuit 4, time constant circuits 5 and 8 and threshold processing circuits 6 and 9.

Abstract: A signal transmission system has a modulation signal converter 1 that generates a modulation signal using a Manchester code with a duty ratio of 50% in accordance with transmission data; a clock generator 6 that generates a clock with the amount of delay with respect to the rising or falling edge of the modulation signal; and a data detector 5 that generates received data by sampling the modulation signal in synchronization with the clock. Since the modulation signal converter 1 generates the modulation signal by combining the Manchester code with the duty ratio of 50%, its duty ratio is always 50% independently of the transmission data, thereby preventing the DC offset of the modulation signal on the receiving side. Accordingly, it offers an advantage of achieving good communication quality with a simple circuit configuration without producing the DC offset in the modulation signal on the receiving side.

Abstract: A first clock generation circuit 21 generates a first clock rising at the time which is delayed by ?T (0.5<?<1.0) from the transition point of each data of a received signal having a time period of T which is Manchester-encoded. A second clock generation circuit 22 generates a second clock rising at the time which is delayed by ?T (0.5<?<1.0) from the transition point, ?T being different from ?T. A data detection circuit 31 outputs first and second detection results of the received signal on the basis of the first and second clocks, and a determination circuit 41 performs determination on the received signal on the basis of the first and second detection results.

Abstract: A laser radar system includes: a scanner for transmitting a pulse toward a target while two-dimensionally scanning a transmitting beam, and outputting scan angle information; a lens of the receiver for receiving received light; a high aspect photo detector array for converting the received light into a received signal; a transimpedance amplifier array for amplifying the received signal; an adder circuit for adding the received signal from each element of the transimpedance amplifier array; a distance detecting circuit for measuring a light round-trip time to the target of an output signal from the adder circuit; and a signal processing unit for causing the scanner to perform a two-dimensional scanning operation in association with the scan angle information, to determine distances to multiple points on the target based on the light round-trip time and a speed of light and measure a three-dimensional shape of the target.

Abstract: A signal transmission system has a modulation signal converter 1 that generates a modulation signal using a Manchester code with a duty ratio of 50% in accordance with transmission data; a clock generator 6 that generates a clock with the amount of delay with respect to the rising or falling edge of the modulation signal; and a data detector 5 that generates received data by sampling the modulation signal in synchronization with the clock. Since the modulation signal converter 1 generates the modulation signal by combining the Manchester code with the duty ratio of 50%, its duty ratio is always 50% independently of the transmission data, thereby preventing the DC offset of the modulation signal on the receiving side. Accordingly, it offers an advantage of achieving good communication quality with a simple circuit configuration without producing the DC offset in the modulation signal on the receiving side.

Abstract: Besides a time constant circuit 5 that imposes a frequency limit on a wireless signal detected by a power detecting circuit 4 at a preset time constant Ta, there is provided a time constant circuit 8 that imposes a frequency limit on the wireless signal at a time constant Tb greater than the time constant Ta. When the signal level of an intermittent operation signal supplied from a signal input terminal 1 is H level or when a threshold processing circuit 6 decides that the level of the wireless signal is higher than a threshold Th, a logic unit 3 supplies a control signal that instructs starting to the power detecting circuit 4, time constant circuits 5 and 8 and threshold processing circuits 6 and 9.

Abstract: A laser radar system includes: a scanner for transmitting a pulse toward a target while two-dimensionally scanning a transmitting beam, and outputting scan angle information; a lens of the receiver for receiving received light; a high aspect photo detector array for converting the received light into a received signal; a transimpedance amplifier array for amplifying the received signal; an adder circuit for adding the received signal from each element of the transimpedance amplifier array; a distance detecting circuit for measuring a light round-trip time to the target of an output signal from the adder circuit; and a signal processing unit for causing the scanner to perform a two-dimensional scanning operation in association with the scan angle information, to determine distances to multiple points on the target based on the light round-trip time and a speed of light and measure a three-dimensional shape of the target.