Patents by Inventor Akihito Yamamoto
Akihito Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7888730Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.Type: GrantFiled: March 19, 2007Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
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Publication number: 20110012190Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.Type: ApplicationFiled: September 22, 2010Publication date: January 20, 2011Inventors: Masayuki Tanaka, Daisuke Nishida, Ryota Fujitsuka, Katsuyuki Sekine, Akihito Yamamoto, Katsuaki Natori, Yoshio Ozawa
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Patent number: 7803682Abstract: A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.Type: GrantFiled: August 21, 2007Date of Patent: September 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Katsuaki Natori, Masayuki Tanaka, Akihito Yamamoto
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Publication number: 20100197130Abstract: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.Type: ApplicationFiled: April 7, 2010Publication date: August 5, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yoshio OZAWA, Isao Kamioka, Junichi Shiozawa, Akihito Yamamoto, Ryota Fujitsuka, Yoshihiro Ogawa, Katsuaki Natori, Katsuyuki Sekine, Masayuki Tanaka, Daisuke Nishida
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Publication number: 20100171164Abstract: A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.Type: ApplicationFiled: March 17, 2010Publication date: July 8, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Ichiro Mizushima, Takashi Nakao, Akihito Yamamoto, Takashi Suzuki, Masahiro Kiyotoshi
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Publication number: 20100136780Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the second insulating film comprises forming an insulating film containing silicon using source gas not containing chlorine, and forming an insulating film containing oxygen and a metal element on the insulating film containing silicon.Type: ApplicationFiled: January 12, 2010Publication date: June 3, 2010Inventors: Katsuaki Natori, Masayuki Tanaka, Akihito Yamamoto, Katsuyuki Sekine, Ryota Fujitsuka, Daisuke Nishida, Yoshio Ozawa
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Patent number: 7723772Abstract: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.Type: GrantFiled: January 30, 2007Date of Patent: May 25, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Isao Kamioka, Junichi Shiozawa, Akihito Yamamoto, Ryota Fujitsuka, Yoshihiro Ogawa, Katsuaki Natori, Katsuyuki Sekine, Masayuki Tanaka, Daisuke Nishida
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Publication number: 20100106368Abstract: A damping force control apparatus includes a damping force control device controlling a damping force of a shock absorber provided between a sprung mass and an unsprung mass of each wheel of a vehicle, a detection device detecting at least an acceleration of the sprung mass in an up-down direction and a relative displacement between the sprung mass and the unsprung mass, a damping coefficient calculation device calculating a damping coefficient to be applied to the damping force control by the damping force control device based on detected results of the detection device, a sensed acceleration increment calculation device calculating a sensed acceleration increment corresponding to an increment of sense according to the Weber Fechner law on the basis of the detected results of the detection device, and a modification device modifying the damping coefficient in accordance with a sensed acceleration increment calculated by the sensed acceleration increment calculation device.Type: ApplicationFiled: October 26, 2009Publication date: April 29, 2010Applicant: AISIN SEIKI KABUSHIKI KAISHAInventors: Seiji HIDAKA, Akihito Yamamoto
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Publication number: 20100073449Abstract: In a consecutive processing in which an inkjet printer A consecutively performs printing on a plurality of media sheets and cutting the front ends and the rear ends of the media sheets, a feed interval between any two consecutive media sheets in a cutting section is set larger than that in a printing section.Type: ApplicationFiled: September 14, 2009Publication date: March 25, 2010Applicant: NORITSU KOKI CO., LTD.Inventors: Akihito Yamamoto, Yoshitsugu Tokai
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Patent number: 7682899Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the second insulating film comprises forming an insulating film containing silicon using source gas not containing chlorine, and forming an insulating film containing oxygen and a metal element on the insulating film containing silicon.Type: GrantFiled: March 27, 2007Date of Patent: March 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Katsuaki Natori, Masayuki Tanaka, Akihito Yamamoto, Katsuyuki Sekine, Ryota Fujitsuka, Daisuke Nishida, Yoshio Ozawa
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Patent number: 7635891Abstract: A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control electrode containing metal or metal silicide provided on the charge storage layer via the second insulating film, wherein a corner of a lower part of the control electrode includes semiconductor and fails to contain the metal or the metal silicide in a channel width direction view of the memory cell.Type: GrantFiled: November 28, 2007Date of Patent: December 22, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Katsuaki Natori, Katsuyuki Sekine, Daisuke Nishida, Ryota Fujitsuka, Masayuki Tanaka, Kazuaki Nakajima, Yoshio Ozawa, Akihito Yamamoto
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Patent number: 7635890Abstract: A semiconductor device includes a semiconductor substrate, a plurality of nonvolatile memory cells provided on the semiconductor substrate, each of the plurality of nonvolatile memory cells comprising a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a control gate electrode provided above the charge storage layer, a second insulating film provided between the control gate electrode and the charge storage layer, the second insulating film between adjacent charge storage layers including a first region having permittivity lower than that of the second insulating film on a top surface of the charge storage layer in a cross-section view of a channel width direction of the nonvolatile memory cell, and the first region having composition differing from that of the second insulating film on the top surface of the charge storage layer.Type: GrantFiled: April 13, 2007Date of Patent: December 22, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Akihito Yamamoto, Masayuki Tanaka, Katsuaki Natori, Katsuyuki Sekine, Daisuke Nishida, Ryota Fujitsuka
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Patent number: 7612404Abstract: A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and having higher permittivity than the first insulating film, the interelectrode insulating film being provided on a side wall of the floating gate electrode in a cross-section view of a channel width direction of the cell, thickness of the interelectrode insulating film increasing from an upper portion of the side wall toward a lower portion of the side wall, thickness of the second insulating film on an upper corner of the FG electrode being thicker than thickness of the second insulating film on the other portions of the side wall in the cross-section view of the channel width direction.Type: GrantFiled: April 13, 2007Date of Patent: November 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Akihito Yamamoto, Masayuki Tanaka, Katsuyuki Sekine, Daisuke Nishida, Ryota Fujisuka, Katsuaki Natori, Hirokazu Ishida, Yoshio Ozawa
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Publication number: 20090245913Abstract: Printing paper is cut by moving the lower one of a pair of upper and lower cutting blades with the upper one fixed. A protective member for preventing the printed surface of the printing paper being conveyed from coming into contact with the cutting edge of the upper cutting blade is disposed upstream of the upper cutting blade in the direction of paper conveyance.Type: ApplicationFiled: March 13, 2009Publication date: October 1, 2009Applicant: NORITSU KOKI CO., LTD.Inventor: Akihito YAMAMOTO
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Publication number: 20090190983Abstract: A decurling mechanism moves a decurling roller around a conveyance roller by means of a position changing roller to change the relative position of the decurling roller to the conveyance roller to a decurling position in which a piece of paper web is conveyed while being decurled and a conveyance position in which a paper sheet is conveyed without being decurled. In this case, the clearance between the decurling roller and the conveyance roller when the decurling roller is in the decurling position is set to be larger than that when the decurling roller is in the conveyance position.Type: ApplicationFiled: January 26, 2009Publication date: July 30, 2009Applicant: NORITSU KOKI CO., LTD.Inventors: Akihito YAMAMOTO, Yoshitsugu TOKAI
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Publication number: 20090190985Abstract: A decurling mechanism for performing a decurling process of correcting the curl of paper includes: a first roller; a second roller disposed travelably around the first roller; and a roller position changing mechanism for changing the second roller to a plurality of positions set on a traveling path of the second roller. The plurality of positions include a decurling position in which the decurling process to the paper is enabled and the paper is conveyed while being pinched between the first and second rollers, a conveyance position in which the decurling process to the paper is disabled and the paper is conveyed while being pinched between the first and second rollers and a pinch release position in which the paper is released from the pinch between the first and second rollers.Type: ApplicationFiled: January 27, 2009Publication date: July 30, 2009Applicant: NORITSU KOKI CO., LTD.Inventors: Akihito YAMAMOTO, Yoshitsugu TOKAI
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Publication number: 20090190984Abstract: A decurling mechanism is configured so that a position changing roller moves a decurling roller among a plurality of decurling positions from the weakest decurling position to the strong decurling position. In this manner, the decurling force applied to each piece of paper web is set large when the piece of paper web has a length not smaller than a predetermined value, but set small when the piece of paper web has a length smaller than the predetermined value.Type: ApplicationFiled: January 27, 2009Publication date: July 30, 2009Applicant: NORITSU KOKI CO., LTD.Inventors: Akihito YAMAMOTO, Yoshitsugu TOKAI
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Publication number: 20090190982Abstract: In a printing system, a position changing element moves a decurling roller around a conveyance roller to switch the position of the decurling roller relative to the conveyance roller at least between a decurling position in which a paper web is conveyed while being decurled and a conveyance position in which paper is conveyed without being decurled, and positions the decurling roller in the conveyance position when the conveyance of the paper is stopped.Type: ApplicationFiled: January 26, 2009Publication date: July 30, 2009Applicant: NORITSU KOKI CO., LTD.Inventor: Akihito YAMAMOTO
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Publication number: 20090189337Abstract: A paper output mechanism includes: a roller pair composed of a first roller and a second roller travelable around the first roller and configured, when the second roller is in a first position, to output a piece of paper to a paper placement part by pinching the piece of paper between the first and second rollers and driving at least one of the first and second rollers into rotation with an actuator; and a roller position changing mechanism for switching the second roller between the first position and a second position located closer to the paper output side than the first position. When the trailing edge of the piece of paper is sent out to the paper placement part, the roller position changing mechanism changes the second roller from the first position to the second position.Type: ApplicationFiled: January 27, 2009Publication date: July 30, 2009Applicant: NORITSU KOKI CO., LTD.Inventor: Akihito YAMAMOTO
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Publication number: 20090059372Abstract: Disclosed is an optical image stabilizer having a low sliding load, a smooth operation, and a small thickness. When a lens holder and an X slider are moved in the X direction, small balls roll between the side surface of the lens holder and the inner surface of a frame of a Y slider, thereby reducing a sliding load therebetween. When the lens holder and the Y slider are moved in the X direction, small balls roll between the side surface of the lens holder and the inner surface of the frame of the X slider, thereby reducing a sliding load therebetween. Therefore, it is possible to achieve an optical image stabilizer having low power consumption, a smooth operation, and high responsibility. In addition, the thickness of the lens holder is equal to or smaller than the sum of the thicknesses of the X slider and the Y slider overlapped with each other. Therefore, it is possible to achieve an optical image stabilizer having a small thickness.Type: ApplicationFiled: August 26, 2008Publication date: March 5, 2009Applicant: ALPS ELECTRIC CO., LTDInventors: Takahiro Kawauchi, Akihito Yamamoto, Toru Sawada