Patents by Inventor Akiko Honjo

Akiko Honjo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252437
    Abstract: An imaging device includes a plurality of light-receiving elements arranged in a two-dimensional matrix shape. Each of the light-receiving elements includes a first electrode, a photoelectric conversion layer, and a second electrode. The photoelectric conversion layer has a laminated structure in which a first compound semiconductor layer having a first conductivity type and a second compound semiconductor layer having a second conductivity type that is a reverse conductivity type to the first conductivity type are laminated from a side of the first electrode. The second compound semiconductor layer has been removed in a region between the light-receiving elements. The first electrode and the first compound semiconductor layer are shared by the light-receiving elements. An impurity concentration of a first compound semiconductor layer near the first electrode is lower than that of a first compound semiconductor layer near the second compound semiconductor layer.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shiro UCHIDA, Akiko HONJO, Tomomasa WATANABE, Hideshi ABE
  • Patent number: 10304884
    Abstract: An imaging device includes a plurality of light-receiving elements arranged in a two-dimensional matrix shape. Each of the light-receiving elements includes a first electrode, a photoelectric conversion layer, and a second electrode. The photoelectric conversion layer has a laminated structure in which a first compound semiconductor layer having a first conductivity type and a second compound semiconductor layer having a second conductivity type that is a reverse conductivity type to the first conductivity type are laminated from a side of the first electrode. The second compound semiconductor layer has been removed in a reg between the light-receiving elements. The first electrode and the first compound semiconductor layer are shared by the light-receiving elements. An impurity concentration of a first compound semiconductor layer near the first electrode is lower than that of a first compound semiconductor layer near the second compound semiconductor layer.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: May 28, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shiro Uchida, Akiko Honjo, Tomomasa Watanabe, Hideshi Abe
  • Publication number: 20190035902
    Abstract: The present technology relates to a semiconductor device, a manufacturing method of a semiconductor device, a solid-state imaging device, and an electronic device capable of reducing a parasitic capacitance between a gate electrode and source/drain electrodes and reducing a leakage current. The semiconductor device includes a first impurity region formed between element isolation regions on both sides, a gate electrode formed on an upper surface of a semiconductor substrate where the element isolation regions and the first impurity region are formed so that both ends are respectively overlapped with the element isolation regions on both sides and the gate electrode is separated from the first impurity region by a predetermined distance along a planar direction, and a second impurity region formed on the semiconductor substrate between the gate electrode and the first impurity region in plan view as having the same conductivity type as the first impurity region.
    Type: Application
    Filed: January 6, 2017
    Publication date: January 31, 2019
    Applicant: SONY CORPORATION
    Inventor: Akiko HONJO
  • Publication number: 20180358387
    Abstract: Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 13, 2018
    Inventor: Akiko Honjo
  • Publication number: 20180219039
    Abstract: An imaging device includes a plurality of light-receiving elements 10 arranged in a two-dimensional matrix shape. Each of the light-receiving elements 10 includes a first electrode 31, a photoelectric conversion layer 20, and a second electrode 32. The photoelectric conversion layer 20 has a laminated structure in which a first compound semiconductor layer 21 having a first conductivity type and a second compound semiconductor layer 22 having a second conductivity type that is a reverse conductivity type to the first conductivity type are laminated from a side of the first electrode. The second compound semiconductor layer has been removed in a region 11 between the light-receiving elements 10. The first electrode 31 and the first compound semiconductor layer 21 are shared by the light-receiving elements. An impurity concentration of a first compound semiconductor layer 21A near the first electrode is lower than that of a first compound semiconductor layer 21B near the second compound semiconductor layer.
    Type: Application
    Filed: May 6, 2016
    Publication date: August 2, 2018
    Inventors: Shiro UCHIDA, Akiko HONJO, Tomomasa WATANABE, Hideshi ABE
  • Patent number: 10014324
    Abstract: Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: July 3, 2018
    Assignee: Sony Corporation
    Inventor: Akiko Honjo
  • Patent number: 9406816
    Abstract: Provided is a solid-state imaging apparatus including: a plurality of photoelectric conversion units; an element isolation unit that performs element isolation between the plurality of photoelectric conversion units; and a diffusion prevention unit that prevents diffusion of a dark current component generated on an interfacial surface of the element isolation unit to a region surrounding the dark current component generation region.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: August 2, 2016
    Assignee: SONY CORPORATION
    Inventor: Akiko Honjo
  • Publication number: 20160020327
    Abstract: A semiconductor device includes: an oxide semiconductor film; a gate insulating film; and a gate electrode, the oxide semiconductor film, the gate insulating film, and the gate electrode being provided in this order on a substrate, in which a thick-film section is provided in one or both of end portions of the gate insulating film, the thick-film section having a larger thickness than a thickness of a portion other than the thick-film section of the gate insulating film.
    Type: Application
    Filed: June 15, 2015
    Publication date: January 21, 2016
    Inventors: Shinya Yamakawa, Akiko Honjo
  • Publication number: 20150171113
    Abstract: Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.
    Type: Application
    Filed: October 30, 2014
    Publication date: June 18, 2015
    Inventor: Akiko Honjo
  • Patent number: 8975667
    Abstract: A solid-state imaging device including, active elements configured to handle the charge captured in a photoreceiving region, an element isolation region configured to isolate regions of the active element, a first impurity region configured to surround the element isolation region, and a second impurity region including an impurity region lower in impurity concentration than the first impurity region, the second impurity region being provided between the first impurity region and active elements.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 10, 2015
    Assignee: Sony Corporation
    Inventors: Akiko Honjo, Shinya Yamakawa
  • Publication number: 20130099094
    Abstract: A solid-state imaging device including, active elements configured to handle the charge captured in a photoreceiving region, an element isolation region configured to isolate regions of the active element, a first impurity region configured to surround the element isolation region, and a second impurity region including an impurity region lower in impurity concentration than the first impurity region, the second impurity region being provided between the first impurity region and active elements.
    Type: Application
    Filed: September 14, 2012
    Publication date: April 25, 2013
    Applicant: SONY CORPORATION
    Inventors: Akiko Honjo, Shinya Yamakawa
  • Publication number: 20100224759
    Abstract: Disclosed herein is a solid-state imaging device including, active elements configured to handle the charge captured in a photoreceiving region, an element isolation region configured to isolate regions of the active element, a first impurity region configured to surround the element isolation region, and a second impurity region including an impurity region lower in impurity concentration than the first impurity region, the second impurity region being provided between the first impurity region and active elements.
    Type: Application
    Filed: February 25, 2010
    Publication date: September 9, 2010
    Applicant: SONY CORPORATION
    Inventors: Akiko Honjo, Shinya Yamakawa