Abstract: A bicycle electrical system diagnostic device is provided for a bicycle electrical system in which several electric devices are connected. The diagnostic device includes a connecting section and an electric device recognizing section. The connecting section is configured to be connected to and disconnected from the electrical system. The electric device recognizing section is configured to communicate with the electrical system and recognize any of the electric devices while the connecting section is electrically connected to anyone of the electric devices.

Abstract: The present invention provides bead-like hollow particles and an easy and convenient method for producing the same, and a friction material using the bead-like hollow particles. The particles are bead-like hollow particles comprising odd-shaped particles composed of a metal oxide as a main component and having at least one of a through hole and non-through hole in a surface; the method is a producing method for the bead-like hollow particles, which comprises spraying and drying a suspension of a particulate biological material and a particulate metal oxide by a two-fluid nozzle spray dryer to obtain a powder composed of the particulate biological material as a core and a layer of the particulate metal oxide as a shell, and heating the obtained powder; and the friction material is a friction material using the hollow particles.

Abstract: An object of the present invention is to improve the fluidity of a thermosetting powder adhesive and clear the blocking with a powder adhesive in a constant amount supplying apparatus or a delivery pathway. The present invention has attained the object by a powder adhesive containing a thermosetting adhesive particle and an inorganic filler present on the surface of the thermosetting adhesive particle.

Abstract: Each of a plurality of master devices outputs a speed grade signal indicating a data transfer speed with a data transfer request. An arbiter arbitrates transfer requests and speed grade signals from the plurality of master devices. A clock enable generation circuit generates a clock enable signal with a varying ratio of a valid level according to the speed grade signal arbitrated by the arbiter. A slave device operates upon receiving a clock signal when the clock enable signal is at the valid level, and transfers data according to the transfer request arbitrated by the arbiter. Accordingly, the frequency of the clock signal which causes the slave device to operate may be changed for each transfer request, and a fine control of the power of the slave device may be easily performed. As a result, power consumption of the data processing system may be finely controlled.

Abstract: To provide a digital data transmitting apparatus and a digital data receiving apparatus that can realize, even when a transmission channel characteristic changes because of aged deterioration or the like of a relay, improvement of a reception performance following the change. A transmitting apparatus 1 generates a multiplexing frame formed by N slots including control information, data, outer parities, stuff bits, and inner parities and added with synchronization, pilot, and a transmission control signal and a parity and transmits data of the respective slots in a Transmission system designated by the transmission control signal. In this case, pilot signals are symbols allocated to all signal points in order determined in advance for each of modulation schemes. A receiving apparatus 2 rewrites a phase error table 214 to calculate a phase error and performs synchronous detection according to the pilot signals. The receiving apparatus 2 also rewrites a likelihood table 235 to perform inner code decoding.

Abstract: To provide a digital data transmitting apparatus and a digital data receiving apparatus that can realize, even when a transmission channel characteristic changes because of aged deterioration or the like of a relay, improvement of a reception performance following the change. A transmitting apparatus 1 generates a multiplexing frame formed by N slots including control information, data, outer parities, stuff bits, and inner parities and added with synchronization, pilot, and a transmission control signal and a parity and transmits data of the respective slots in a transmission system designated by the transmission control signal. In this case, pilot signals are symbols allocated to all signal points in order determined in advance for each of modulation schemes. A receiving apparatus 2 rewrites a phase error table 214 to calculate a phase error and performs synchronous detection according to the pilot signals. The receiving apparatus 2 also rewrites a likelihood table 235 to perform inner code decoding.

Abstract: A memory control device for controlling an access from a processing unit to a cache memory, the memory control device includes: an address estimation circuit for receiving a first read address of the cache memory from the processing unit and estimating a second read address on the basis of the first read address; an access start detection circuit for detecting an access start of accessing cache memory at the first read address and outputting an access start signal; a data control circuit for receiving read data from the cache memory and for outputting the read data to the processing unit; and a clock control circuit for controlling a read clock to be output to the processing unit in response to the access start signal, the processing unit receiving the read data from the data control circuit with the read clock.

Abstract: A method for producing a solid lubricant includes steps of preparing and coating. A phosphate aqueous solution prepared by the step of preparing is an aqueous solution containing at least one of aluminum dihydrogen phosphate and magnesium dihydrogen phosphate in an amount of 0.5 to 10% by mass. A graphite material is coated with a phosphate using the phosphate aqueous solution. The graphite material is used at a ratio of 40 to 50 parts by mass based on 100 parts by mass of the aqueous solution.

Abstract: An information processing system includes a master module for outputting a transfer state signal in correspondence to a data read instruction when the data read instruction is successively output plural times, the transfer state signal indicating that at least one data read instruction succeeds some one of the data read instructions; and a memory controller for, when receiving the some one of the data read instructions and the corresponding transfer state signal from the master module, supplying data corresponding to the some one of the data read instructions to the master module, while reading data corresponding to the at least one data read instruction, which succeeds the some one of the data read instructions, from a memory and holding the read data in accordance with the received transfer state signal.

Abstract: An iron member having a coating film on at least part of its surface is manufactured by a step of projecting zinc particles to the surface of a base material made of an iron material to form a base film, and a step of forming a coating film of resin coating material on at least a part of the base film.

Abstract: To provide a digital data transmitting apparatus and a digital data receiving apparatus that can realize, even when a transmission channel characteristic changes because of aged deterioration or the like of a relay, improvement of a reception performance following the change. A transmitting apparatus 1 generates a multiplexing frame formed by N slots including control information, data, outer parities, stuff bits, and inner parities and added with synchronization, pilot, and a transmission control signal and a parity and transmits data of the respective slots in a transmission system designated by the transmission control signal. In this case, pilot signals are symbols allocated to all signal points in order determined in advance for each of modulation schemes. A receiving apparatus 2 rewrites a phase error table 214 to calculate a phase error and performs synchronous detection according to the pilot signals. The receiving apparatus 2 also rewrites a likelihood table 235 to perform inner code decoding.

Abstract: An iron member having a coating film on at least part of its surface is manufactured by a step of projecting zinc particles to the surface of a base material made of an iron material to form a base film, and a step of forming a coating film of resin coating material on at least a part of the base film.

Abstract: A digital demodulator which will need no absolute phasing circuit is provided.

Abstract: After receiving a time division multiplex signal including a plurality of digital data signals transmitted in accordance with different transmission schemes, the received time division multiplex signal is demodulated by a demodulation circuit, and it is judged by a detection circuit whether each of the demodulated digital data signals is received correctly or not. When it is detected that a digital data signal transmitted by any one of the plurality of different transmission schemes is not received correctly, the relevant digital data signal is replaced by a suitable signal such as a null packet signal which does not affect a correct reception of the remaining digital data signals transmitted by the remaining transmission schemes to form a corrected time division multiplexed signal even if a digital data signal is not received correctly.

Abstract: A digital broadcasting receiver is provided which can reproduce a carrier quickly and capture a desired signal at high speed. A carrier reproduction phase error detection circuit (6) detects a phase error voltage in accordance with a demodulation output obtained by demodulating a demodulated wave of a modulated wave during a predetermined section in a header section. A peak number calculation circuit (92) calculates an error frequency between a desired reception frequency and a reproduction carrier frequency in accordance with the phase error voltage. A differential coefficient calculation circuit (94) calculates the polarity of the error frequency. A step frequency control circuit (96) converts the calculated error frequency having the calculated polarity into a step frequency width for automatic frequency control. The reproduction carrier frequency is scanned at the converted step frequency width until a frame sync is established after the frame sync is detected.

Abstract: A receiver is constructed so that it detects a short-break of a digital broadcasting wave by the absence of a synchronizing code or by a transmission control signal multiplexed with the broadcasting wave and, according to the short-break detection signal, holds data and state information (program arrangement, and reference time information) obtained by an antenna and converter (1), tuner and digital decoding portion (2), an error correction code decoding portion (3), a stream multiplexed signal separating portion (4), an audio/video decoding portion (5) and the other components and performs a process for optimally changing characteristics of closed loops for establishing synchronization.

Abstract: A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit (4), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180°, which are included in a carrier reproduction phase difference detecting circuit (8), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit (10) so that the phase obtained from the signal point position coincides with the phase convergence point.

Abstract: A hierarchical transmission digital demodulator capable of stable sync capture and stable demodulation through setting of a demodulation operation in accordance with a reception C/N value. A CNR measuring circuit receives a demodulation output from an arithmetic circuit and measures a reception C/N value. During a period until sync is captured, a carrier is reproduced in accordance with the demodulation output that a modulated wave in a header section and a modulated wave of burst symbol signal. After sync is captured, at an intermediate C/N value the carrier is reproduced in accordance with the demodulation output of the header section, burst symbol signal and QPSK signal and in accordance with output from a logical gate circuit, and at high and low C/N values the carrier is reproduced by setting high a carrier reproduction loop gain of a gain control circuit in accordance with a signal from the logical gate circuit.

Abstract: A digital demodulator that eliminates the need for an absolute phase circuit is provided. In a digital demodulator for a digital broadcasting receiver that receives digital time-division multiplexed signals of different types of modulation, the demodulated baseband signal is selectively inverted by an inverter (7) according to an inversion command signal “0” or “1” that is output from an inversion decision circuit (6) depending on a BPSK signal of a known pattern. A phase error detector (8) for carrier reproduction determines the phase error voltage based on the phase difference between the absolute phase and the phase of the signal point of the demodulated baseband signal output from the inverter (7). The phase error voltage is passed through a carrier filter (9), including a low-pass filter, to control the carrier frequency so that carrier reproduction can be carried out with the phase at the signal point being coincident with the point of phase convergence.

Abstract: There is provided a synchronization acquiring circuit for stably acquiring frame synchronization without pseudo-synchronization lock when the frame synchronization is acquired in reception at the time of a low C/N. The synchronization pattern of a received frame is detected by a frame synchronization detecting circuit 2. The bits of the synchronization pattern of the received frame are compared with those of a frame synchronization pattern on the transmitting side by a frame synchronizing circuit 5 to obtain the number of coincided bits. The frame synchronization is regarded as detected when the obtained number of bits of each frame is equal to or larger than the correlation detection value.