Abstract: Disclosed is a vehicular headlamp including: a basic lamp unit configured to form a main light distribution pattern that is controlled in light distribution so as to satisfy illuminance requirements at a plurality of predetermined sites in a low beam light distribution pattern which is projected on a vertical virtual screen positioned in front of a vehicle; and a plurality of additional lamp units controlled in light distribution so as to irradiate light to any one of left and right diffusion regions adjacent to the main light distribution pattern. The low beam light distribution pattern is formed on the vertical virtual screen by combining the basic lamp unit and the plurality of additional lamp units.

Abstract: A vehicle headlamp includes at least three lamp units and a controller. Each of the at least three lamp units has a semiconductor light emitting device as a light source. The controller is configured to turn on at least one of the at least three lamp units to form a fog lamp light distribution pattern, and to turn on the at least one of the at least three lamp units and one or more of the at least three lamp units other than the at least one of the at least three lamp units to form a cornering lamp light distribution pattern.

Abstract: In this instrument panel, a groove portion for forming an intended splitting portion in the door main body portion of the airbag door is formed at a cover layer side of the door main body portion. Therefore, when the door main body portion inverts from the recessed shape to a protruding shape due to inflation pressure of an airbag, the groove portion is stretched in the curvature direction of the door main body portion. As a result, stress arising at the intended splitting portion is dispersed, and splitting of the intended splitting portion before the door main body portion has completely inverted to the protruding shape is prevented. Therefore, unintended interference between a front side door portion and a rear side door portion may be prevented.

Abstract: A vehicular headlamp has a projection lens, a light source disposed behind a rear focal point of the projection lens, and a reflector that reflects light from the light source forward. The vehicular headlamp forms a forward light distribution pattern. The vehicular headlamp includes a plate-like shade having a front-end portion positioned in the vicinity of the rear focal point of the projection lens to form a cut-off line of the forward light distribution pattern. The shade extends rearward and obliquely downward from the front-end portion. An overhead sign reflective surface is provided on a lower surface of the shade. The overhead sign reflective surface reflects light from the reflector toward the projection lens to form a part of an overhead sign distribution pattern.

Abstract: A vehicle head lamp includes: a light source; a reflector that reflects light emitted from the light source; a condenser lens that irradiates the light reflected by the reflector forward; and a shade that blocks part of the light reflected by the reflector to obtain a desired light distribution. The shade includes a main shade that has an opening for passing overhead sign light irradiated forward and upward and a sub-shade that is provided so as to be inclined rearward and downward from an upper edge of the main shade in order to obtain a cut line of the light distribution, and the reflector has an OHS reflection area used to project part of the reflected light toward a lower surface of the sub-shade and that allows the light reflected on the lower surface to pass through the opening of the main shade as the OHS light.

Abstract: A vehicle lamp is provided with: a projection lens; a light source; a reflector that reflects light from the light source to the projection lens; and a shade member. A shade member includes an opening, and a portion of an inner peripheral edge of the opening is defined by an upper edge of a shading part for shielding a portion of the light reflected on the reflector. A side end portion of a reflection surface of the reflector penetrates the opening of the shade member and extends forward beyond the shading part.

Abstract: A sampling clock generator generates a sampling clock based on a reference clock and an internal clock. An internal clock generator causes, during a period in which the sampling clock is at a second voltage level, the internal clock to transition from a first voltage level to a second voltage level when a first comparison signal and a second comparison signal transition to voltage levels different from each other, and the internal clock to transition from the second voltage level to the first voltage level after a variable delay time has elapsed when the first and second comparison signals transition to a same voltage level. A delay controller controls the variable delay time in the internal clock generator so that the ratio of a period in which the sampling clock is at a first voltage level to a period of the reference clock approaches a predetermined ratio.

Abstract: A controller controls first and second supply switches so that, during a sampling period, a ground voltage is supplied to n first up-capacitors and n second up-capacitors while a power supply voltage is supplied to n first down-capacitors and n second down-capacitors. The controller also controls the first and second supply switches based on the result of comparison by a comparator during each of n bit determination periods so that a first analog voltage at a first sampling node and a second analog voltage at a second sampling node gradually approach each other.

Abstract: An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.

Abstract: A method for cutting a brittle-material substrate by irradiating a converged laser beam on a brittle-material substrate along first and second cutting lines intersecting each other at least at one point, includes forming scribe lines along the first and the second cutting lines on a surface of the brittle-material substrate, and relatively moving an irradiation position of the laser beam on the surface of the brittle-material substrate along the scribe lines to cut the brittle-material substrate at a forward position of the irradiation position in the moving direction of the irradiation position. The irradiation of the laser beam is limited in a region in the vicinity of an intersection where the first and the second cutting lines intersect.

Abstract: A vehicle lighting apparatus is provided with: a light source device including a first light source and a second light source; a reflector adapted to reflect forwardly light emitted from the light sources; a main shade adapted to shade a portion of light emitted from the first light source and reflected by the reflector; and a sub shade adapted to shade at least a portion of light emitted from the second light source and reflected by the reflector.

Abstract: In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.

Abstract: Provide a process for cutting a brittle-material plate, a window glass for vehicles obtained by the cutting process, and a system for cutting such a brittle-material plate, which are capable of cutting such a brittle-material plate in a desired planar shape in production with an automatic machine being utilized therein without making the cutting system complicated. The process for cutting such a brittle-material plate includes a first step for forming a scribe line L2 on a top surface G1 of the plate G, and a second step for relatively moving the irradiation position A of the laser beam on the top surface G1 of the plate G along the scribe line L2 to cut the plate ahead of the irradiation position in the moving direction of the plate.

Abstract: A vehicle head lamp includes: a light source; a reflector that reflects light emitted from the light source; a condenser lens that irradiates the light reflected by the reflector forward; and a shade that blocks part of the light reflected by the reflector to obtain a desired light distribution. The shade includes a main shade that has an opening for passing overhead sign light irradiated forward and upward and a sub-shade that is provided so as to be inclined rearward and downward from an upper edge of the main shade in order to obtain a cut line of the light distribution, and the reflector has an OHS reflection area used to project part of the reflected light toward a lower surface of the sub-shade and that allows the light reflected on the lower surface to pass through the opening of the main shade as the OHS light.

Abstract: An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.

Abstract: In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.

Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Abstract: Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.

Abstract: A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.

Abstract: Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0 to LS7) are equal to each other.