Patents by Inventor Akinori Nakano
Akinori Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230040728Abstract: Provided are a substrate processing apparatus and a substrate processing method capable of achieving uniform trimming throughout an entire surface of a substrate. The substrate processing apparatus includes a gas channel including a center gas inlet and an additional gas inlet spaced apart from the center gas inlet, and a shower plate including a plurality of holes connected to the center gas inlet and the additional gas inlet, wherein a gas flow channel is formed having a clearance defined by a lower surface of the gas channel and an upper surface of the shower plate, the lower surface and the upper surface being substantially parallel.Type: ApplicationFiled: October 19, 2022Publication date: February 9, 2023Inventors: Akinori Nakano, Toshihisa Nozawa, Ryu Nakano
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Patent number: 11482418Abstract: Provided are a substrate processing apparatus and a substrate processing method capable of achieving uniform trimming throughout an entire surface of a substrate. The substrate processing apparatus includes a gas channel including a center gas inlet and an additional gas inlet spaced apart from the center gas inlet, and a shower plate including a plurality of holes connected to the center gas inlet and the additional gas inlet, wherein a gas flow channel is formed having a clearance defined by a lower surface of the gas channel and an upper surface of the shower plate, the lower surface and the upper surface being substantially parallel.Type: GrantFiled: March 19, 2018Date of Patent: October 25, 2022Assignee: ASM IP Holding B.V.Inventors: Akinori Nakano, Toshihisa Nozawa, Ryu Nakano
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Publication number: 20190259611Abstract: Provided are a substrate processing apparatus and a substrate processing method capable of achieving uniform trimming throughout an entire surface of a substrate. The substrate processing apparatus includes a gas channel including a center gas inlet and an additional gas inlet spaced apart from the center gas inlet, and a shower plate including a plurality of holes connected to the center gas inlet and the additional gas inlet, wherein a gas flow channel is formed having a clearance defined by a lower surface of the gas channel and an upper surface of the shower plate, the lower surface and the upper surface being substantially parallel.Type: ApplicationFiled: March 19, 2018Publication date: August 22, 2019Inventors: Akinori Nakano, Toshihisa Nozawa, Ryu Nakano
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Patent number: 9899291Abstract: A method for protecting a layer includes: providing a substrate having a target layer and forming a protective layer on the target layer, said protective layer contacting and covering the target layer and containing a hydrocarbon-based layer constituting at least an upper part of the protective layer, which hydrocarbon-based layer is formed by plasma-enhanced atomic layer deposition (PEALD) using an alkylaminosilane precursor and a noble gas without a reactant.Type: GrantFiled: July 13, 2015Date of Patent: February 20, 2018Assignee: ASM IP HOLDING B.V.Inventors: Richika Kato, Seiji Okuro, Kunitoshi Namba, Yuya Nonaka, Akinori Nakano
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Publication number: 20170018477Abstract: A method for protecting a layer includes: providing a substrate having a target layer and forming a protective layer on the target layer, said protective layer contacting and covering the target layer and containing a hydrocarbon-based layer constituting at least an upper part of the protective layer, which hydrocarbon-based layer is formed by plasma-enhanced atomic layer deposition (PEALD) using an alkylaminosilane precursor and a noble gas without a reactant.Type: ApplicationFiled: July 13, 2015Publication date: January 19, 2017Inventors: Richika Kato, Seiji Okuro, Kunitoshi Namba, Yuya Nonaka, Akinori Nakano
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Patent number: 9478414Abstract: A method is for hydrophobization of a surface of a silicon-containing film by atomic layer deposition (ALD), wherein the surface is subjected to atmospheric exposure. The method includes: (i) providing a substrate with a silicon-containing film formed thereon; and (ii) forming on a surface of the silicon-containing film a hydrophobic atomic layer as a protective layer subjected to atmospheric exposure, by exposing the surface to a silicon-containing treating gas without exciting the gas. The treating gas is capable of being chemisorbed on the surface to form a hydrophobic atomic layer thereon.Type: GrantFiled: September 26, 2014Date of Patent: October 25, 2016Assignee: ASM IP Holding B.V.Inventors: Akiko Kobayashi, Akinori Nakano, Dai Ishikawa, Kiyohiro Matsushita
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Publication number: 20160093485Abstract: A method is for hydrophobization of a surface of a silicon-containing film by atomic layer deposition (ALD), wherein the surface is subjected to atmospheric exposure. The method includes: (i) providing a substrate with a silicon-containing film formed thereon; and (ii) forming on a surface of the silicon-containing film a hydrophobic atomic layer as a protective layer subjected to atmospheric exposure, by exposing the surface to a silicon-containing treating gas without exciting the gas. The treating gas is capable of being chemisorbed on the surface to form a hydrophobic atomic layer thereon.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Akiko Kobayashi, Akinori Nakano, Dai Ishikawa, Kiyohiro Matsushita
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Patent number: 9190263Abstract: A method for forming a modified low-k SiOCH film on a substrate, includes: providing a low-k SiOCH film formed on a substrate by flowable CVD; exposing the low-k SiOCH film to a gas containing a Si—N bond in its molecule without applying electromagnetic energy to increase Si—O bonds and/or Si—C bonds in the film; and then curing the low-k SiOCH film.Type: GrantFiled: August 22, 2013Date of Patent: November 17, 2015Assignee: ASM IP Holding B.V.Inventors: Dai Ishikawa, Kiyohiro Matsushita, Akinori Nakano, Shintaro Ueda, Hirofumi Arai
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Patent number: 9117657Abstract: A method for filling recesses of a substrate with an insulation film includes: (i) exposing surfaces of the recesses of the substrate to a pre-deposition gas in a reactive state in a reaction space to treat the surfaces with reactive hydrocarbons generated from the pre-deposition gas without filling the recesses; and (ii) depositing a flowable insulation film using a process gas other than the pre-deposition gas on a surface of the substrate to fill the recesses treated in step (i) therewith by plasma reaction. The pre-deposition gas has at least one hydrocarbon unit in its molecule.Type: GrantFiled: June 7, 2013Date of Patent: August 25, 2015Assignee: ASM IP HOLDING B.V.Inventors: Akinori Nakano, Shintaro Ueda
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Patent number: 9029272Abstract: A method for forming a gap-fill SiOCH film on a patterned substrate includes: (i) providing a substrate having recessed features on its surface; (ii) filling the recessed features of the substrate with a SiOCH film which is flowable and non-porous; (iii) after completion of step (ii), exposing the SiOCH film to a plasma including a hydrogen plasma; and (iv) curing the plasma-exposed SiOCH film with UV light.Type: GrantFiled: October 31, 2013Date of Patent: May 12, 2015Assignee: ASM IP Holding B.V.Inventors: Akinori Nakano, Shintaro Ueda, Dai Ishikawa, Kiyohiro Matsushita
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Publication number: 20150118864Abstract: A method for forming a gap-fill SiOCH film on a patterned substrate includes: (i) providing a substrate having recessed features on its surface; (ii) filling the recessed features of the substrate with a SiOCH film which is flowable and non-porous; (iii) after completion of step (ii), exposing the SiOCH film to a plasma including a hydrogen plasma; and (iv) curing the plasma-exposed SiOCH film with UV light.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Applicant: ASM IP Holding B.V.Inventors: Akinori Nakano, Shintaro Ueda, Dai Ishikawa, Kiyohiro Matsushita
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Publication number: 20150056821Abstract: A method for forming a modified low-k SiOCH film on a substrate, includes: providing a low-k SiOCH film formed on a substrate by flowable CVD; exposing the low-k SiOCH film to a gas containing a Si—N bond in its molecule without applying electromagnetic energy to increase Si—O bonds and/or Si—C bonds in the film; and then curing the low-k SiOCH film.Type: ApplicationFiled: August 22, 2013Publication date: February 26, 2015Applicant: ASM IP Holding B.V.Inventors: Dai Ishikawa, Kiyohiro Matsushita, Akinori Nakano, Shintaro Ueda, Hirofumi Arai
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Publication number: 20140363983Abstract: A method for filling recesses of a substrate with an insulation film includes: (i) exposing surfaces of the recesses of the substrate to a pre-deposition gas in a reactive state in a reaction space to treat the surfaces with reactive hydrocarbons generated from the pre-deposition gas without filling the recesses; and (ii) depositing a flowable insulation film using a process gas other than the pre-deposition gas on a surface of the substrate to fill the recesses treated in step (i) therewith by plasma reaction. The pre-deposition gas has at least one hydrocarbon unit in its molecule.Type: ApplicationFiled: June 7, 2013Publication date: December 11, 2014Inventors: Akinori Nakano, Shintaro Ueda
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Patent number: 8551892Abstract: A method for reducing a dielectric constant of a film includes (i) forming a dielectric film on a substrate; (ii) treating a surface of the film without film formation, and (III) curing the film. Step (i) includes providing a dielectric film containing a porous matrix and a porogen on a substrate, step (ii) includes, prior to or subsequent to step (iii), treating the dielectric film with charged species of hydrogen generated by capacitively-coupled plasma without film deposition to reduce a dielectric constant of the dielectric film, and step (iii) includes UV-curing the dielectric film to remove at least partially the porogen from the film.Type: GrantFiled: July 27, 2011Date of Patent: October 8, 2013Assignee: ASM Japan K.K.Inventor: Akinori Nakano
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Publication number: 20130029498Abstract: A method for reducing a dielectric constant of a film includes (i) forming a dielectric film on a substrate; (ii) treating a surface of the film without film formation, and (III) curing the film. Step (i) includes providing a dielectric film containing a porous matrix and a porogen on a substrate, step (ii) includes, prior to or subsequent to step (iii), treating the dielectric film with charged species of hydrogen generated by capacitively-coupled plasma without film deposition to reduce a dielectric constant of the dielectric film, and step (iii) includes UV-curing the dielectric film to remove at least partially the porogen from the film.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: ASM Japan K.K.Inventor: Akinori Nakano
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Patent number: 7884016Abstract: In some embodiments, a low-k dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of through-silicon vias used in three-dimensional (3-D) integration of integrated circuits. A semiconductor workpiece having a via is provided. A dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of the via by chemical vapor deposition. Following the deposition of the dielectric film liner, conductive material is deposited into the via. The conductive material on the bottom of the via can be exposed by thinning the back of the semiconductor workpiece, thereby forming a through-silicon via. The semiconductor workpiece can form a stack with one or more additional semiconductor workpieces having vias filled with conductive material to form a 3-D integrated circuit. The conductive material electrically interconnects the integrated circuits at different levels of the stack.Type: GrantFiled: February 12, 2009Date of Patent: February 8, 2011Assignee: ASM International, N.V.Inventors: Hessel Sprey, Akinori Nakano
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Publication number: 20100200989Abstract: In some embodiments, a low-k dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of through-silicon vias used in three-dimensional (3-D) integration of integrated circuits. A semiconductor workpiece having a via is provided. A dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of the via by chemical vapor deposition. Following the deposition of the dielectric film liner, conductive material is deposited into the via. The conductive material on the bottom of the via can be exposed by thinning the back of the semiconductor workpiece, thereby forming a through-silicon via. The semiconductor workpiece can form a stack with one or more additional semiconductor workpieces having vias filled with conductive material to form a 3-D integrated circuit. The conductive material electrically interconnects the integrated circuits at different levels of the stack.Type: ApplicationFiled: February 12, 2009Publication date: August 12, 2010Applicant: ASM International, N.V.Inventors: Hessel Sprey, Akinori Nakano
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Publication number: 20100151151Abstract: A method of forming a low-k film containing silicon and carbon on a substrate by plasma CVD, includes: supplying gas of a precursor having a Si—R—O—R—Si bond into a reaction space in which a substrate is placed; and exciting the gas in the reaction space, thereby depositing a film on the substrate.Type: ApplicationFiled: December 11, 2008Publication date: June 17, 2010Applicant: ASM JAPAN K.K.Inventors: Kiyohiro Matsushita, Akinori Nakano, Ryo Kawaguchi, Yuya Nonaka
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Publication number: 20100003833Abstract: A method of forming a fluorine-containing dielectric film on a substrate by plasma CVD, includes: introducing as a process gas a fluorinated carbon compound having at least two double bonds in its molecule and an unsaturated hydrocarbon compound into a reaction space wherein a substrate is placed; and applying RF power to the reaction space to deposit a fluorine-containing dielectric film on the substrate by plasma CVD.Type: ApplicationFiled: July 1, 2008Publication date: January 7, 2010Applicant: ASM JAPAN K.K.Inventors: Naoto Tsuji, Akinori Nakano
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Patent number: D851633Type: GrantFiled: November 10, 2017Date of Patent: June 18, 2019Assignee: TOA CORPORATIONInventors: Akinori Nakano, Daisuke Higashihara