Patents by Inventor Akio Nishida

Akio Nishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200402990
    Abstract: A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second substrate is thinned, and a second silicon oxide surface is provided as a bottommost surface of the second semiconductor die. The second semiconductor die is bonded to the first semiconductor die by inducing oxide-to-oxide bonding between the second silicon oxide surface and the first silicon oxide surface. The handle substrate is detached, and inter-die connection via structures are formed through the second substrate and the bonding interface to contact the first metal interconnect structures.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Inventors: Masatoshi NISHIKAWA, Akio NISHIDA
  • Patent number: 10835932
    Abstract: It is an object to prevent adhesion of a processing liquid to a non-processing region of a substrate. In order to achieve the object, a substrate processing apparatus includes a substrate rotating mechanism, a discharging portion for discharging a processing liquid to a substrate, a moving portion for moving a discharging portion, and a controller. The discharging portion starts to discharge the processing liquid at a first position and is moved to a second position. The first position is a position of the discharging portion where a section of a passage of the discharging portion is projected onto a first region, and the second position is a position of the discharging portion where the section of the passage is projected onto a second region. The first region is a region on the peripheral edge side of the substrate from the second region.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: November 17, 2020
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Takayuki Nishida, Akio Hashizume, Junichi Ishii
  • Patent number: 10833100
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 10, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kenji Sugiura, Mitsuteru Mushiga, Yuji Fukano, Akio Nishida
  • Publication number: 20200335512
    Abstract: A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second substrate is thinned, and a second silicon oxide surface is provided as a bottommost surface of the second semiconductor die. The second semiconductor die is bonded to the first semiconductor die by inducing oxide-to-oxide bonding between the second silicon oxide surface and the first silicon oxide surface. The handle substrate is detached, and inter-die connection via structures are formed through the second substrate and the bonding interface to contact the first metal interconnect structures.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 22, 2020
    Inventors: Masatoshi NISHIKAWA, Akio NISHIDA
  • Patent number: 10811058
    Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: October 20, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Zhixin Cui, Akio Nishida, Johann Alsmeier, Yan Li, Steven Sprouse
  • Patent number: 10804202
    Abstract: A first semiconductor die is provided, which includes a first substrate, first semiconductor devices, first interconnect-level dielectric material layers, first metal interconnect structures, and first bonding pads. A second semiconductor die is provided, which includes a semiconductor-on-insulator (SOI) substrate, second semiconductor devices, second interconnect-level dielectric material layers, second metal interconnect structures, and second bonding pads. The second bonding pads are bonded to the first bonding pads. A bulk substrate layer of the SOI substrate is removed exposing an insulating material layer of the SOI substrate, which may be retained or also removed. An external bonding pad is electrically connected to a node of the second semiconductor devices.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: October 13, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Akio Nishida
  • Patent number: 10797060
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou, Srikanth Ranganathan, Akio Nishida, Toshihiro Iizuka
  • Patent number: 10797061
    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akio Nishida, Toshihiro Iizuka, Rahul Sharangpani, Raghuveer S. Makala, Adarsh Rajashekhar, Fei Zhou, Srikanth Ranganathan
  • Patent number: 10797062
    Abstract: A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second substrate is thinned, and a second silicon oxide surface is provided as a bottommost surface of the second semiconductor die. The second semiconductor die is bonded to the first semiconductor die by inducing oxide-to-oxide bonding between the second silicon oxide surface and the first silicon oxide surface. The handle substrate is detached, and inter-die connection via structures are formed through the second substrate and the bonding interface to contact the first metal interconnect structures.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Akio Nishida
  • Patent number: 10797070
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Kenji Sugiura, Akio Nishida
  • Publication number: 20200294918
    Abstract: A first semiconductor die is provided, which includes a first substrate, first semiconductor devices, first interconnect-level dielectric material layers, first metal interconnect structures, and first bonding pads. A second semiconductor die is provided, which includes a semiconductor-on-insulator (SOI) substrate, second semiconductor devices, second interconnect-level dielectric material layers, second metal interconnect structures, and second bonding pads. The second bonding pads are bonded to the first bonding pads. A bulk substrate layer of the SOI substrate is removed exposing an insulating material layer of the SOI substrate, which may be retained or also removed. An external bonding pad is electrically connected to a node of the second semiconductor devices.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 17, 2020
    Inventor: Akio Nishida
  • Publication number: 20200295043
    Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Inventors: Akio Nishida, Mitsuteru Mushiga
  • Publication number: 20200286875
    Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Inventors: Akio NISHIDA, Mitsuteru MUSHIGA, Zhixin CUI
  • Publication number: 20200266146
    Abstract: A first semiconductor die is provided, which includes a first substrate, first semiconductor devices, first interconnect-level dielectric material layers, first metal interconnect structures, and first bonding pads. A second semiconductor die is provided, which includes a semiconductor-on-insulator (SOI) substrate, second semiconductor devices, second interconnect-level dielectric material layers, second metal interconnect structures, and second bonding pads. The second bonding pads are bonded to the first bonding pads. A bulk substrate layer of the SOI substrate is removed exposing an insulating material layer of the SOI substrate, which may be retained or also removed. An external bonding pad is electrically connected to a node of the second semiconductor devices.
    Type: Application
    Filed: February 18, 2019
    Publication date: August 20, 2020
    Inventor: Akio Nishida
  • Publication number: 20200258816
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A pass-through via structure vertically extends through a dielectric material portion that is adjacent to the alternating stack. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A backside bonding pad or bonding wire is formed to be electrically connected to the pass-through via structure.
    Type: Application
    Filed: March 25, 2020
    Publication date: August 13, 2020
    Inventors: Teruo OKINA, Akio NISHIDA, James KAI
  • Publication number: 20200258876
    Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.
    Type: Application
    Filed: April 14, 2020
    Publication date: August 13, 2020
    Inventors: Naohiro HOSODA, Kazuma SHIMAMOTO, Tetsuya SHIRASU, Yuji FUKANO, Akio NISHIDA
  • Publication number: 20200258817
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A pass-through via structure vertically extends through a dielectric material portion that is adjacent to the alternating stack. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A backside bonding pad or bonding wire is formed to be electrically connected to the pass-through via structure.
    Type: Application
    Filed: March 25, 2020
    Publication date: August 13, 2020
    Inventors: Teruo OKINA, Akio NISHIDA, James KAI
  • Patent number: 10741576
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word lines located over a substrate, memory stack structures extending through the alternating stack and containing a respective vertical semiconductor channel and a respective memory film, drain select gate electrodes located over the alternating stack, extending along a first horizontal direction, and laterally spaced apart along a second horizontal direction, and a dielectric cap layer located between adjacent drain select gate electrodes. An air gap is located between adjacent drain select gate electrodes in the dielectric cap layer.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Akio Nishida
  • Publication number: 20200251149
    Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Inventors: Yanli ZHANG, Zhixin CUI, Akio NISHIDA, Johann ALSMEIER, Yan LI, Steven SPROUSE
  • Publication number: 20200235123
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 23, 2020
    Inventors: Kenji SUGIURA, Mitsuteru MUSHIGA, Yuji FUKANO, Akio NISHIDA