Patents by Inventor Akio Shima

Akio Shima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11380764
    Abstract: The purpose of the present invention is to provide a semiconductor device comprising an epitaxial layer formed on a SiC substrate, and a CMOS formed in the top part of the epitaxial layer, wherein growth of any defects present at the interface between the SiC substrate and the epitaxial layer is suppressed, and the reliability of the semiconductor device is improved. As a means to achieve the foregoing, a semiconductor device is formed such that the distance from a p-type diffusion layer to the interface between an n-type epitaxial layer and an n-type semiconductor substrate is larger than the thickness of a depletion layer that extends from the p-type diffusion layer to the back side of the n-type semiconductor substrate in response to the potential difference between a substrate electrode and another substrate electrode.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 5, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Masunaga, Shintaroh Sato, Akio Shima, Digh Hisamoto
  • Patent number: 11349000
    Abstract: An n type semiconductor layer is formed over an n type semiconductor substrate made of silicon carbide, a p type impurity region is formed in the semiconductor layer, and an n type drain region and an n type source region are formed in the impurity region. A field insulating film having an opening that selectively opens a part of the impurity region located between the drain and source regions is formed over the impurity region and the drain and source regions. A gate insulating film is formed over the impurity region in the opening, and a gate electrode is formed on the gate insulating film. Here, a field relaxation layer having an impurity concentration higher than that of the impurity region is formed in at least a part of the impurity region located between the drain and source regions in plan view and located below the field insulating film.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: May 31, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Masunaga, Shintaroh Sato, Akio Shima, Ryo Kuwana, Isao Hara
  • Patent number: 11239314
    Abstract: A MOSFET that has a drain region and a source region on an upper surface of a semiconductor substrate and a gate electrode that is formed on the semiconductor substrate, and an element separation insulating film that includes an opening portion which exposes an active region, on the semiconductor substrate, are formed. At this point, a gate leading-out interconnection that overlaps the element separation insulating film when viewed from above, and that is integrally combined with the gate electrode is formed in a position where the gate leading-out interconnection does not extend over a distance between both the drain region and the source region when viewed from above, on a region that is exposed from the gate electrode.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: February 1, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Masunaga, Akio Shima, Shintaroh Sato, Ryo Kuwana
  • Patent number: 11119228
    Abstract: There is provided a radiation detector using SiC and of a structure in which an electric field is applied to the interior of the entire SiC crystal constituting a radiation sensible layer, aiming to detect radiation while suppressing a reduction in electric signals generated in the radiation sensible layer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: September 14, 2021
    Assignee: HITACHI, LTD.
    Inventors: Norifumi Kameshiro, Akio Shima
  • Publication number: 20210280677
    Abstract: A SiC wafer including a SiC substrate and an epitaxial layer formed on the SiC substrate and containing SiC is provided, and a composition ratio of C—Si of an upper surface of the epitaxial layer is 50 atm % or less.
    Type: Application
    Filed: February 24, 2021
    Publication date: September 9, 2021
    Applicant: HITACHI METALS, LTD.
    Inventors: Keisuke KOBAYASHI, Akio SHIMA
  • Patent number: 11031238
    Abstract: In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: June 8, 2021
    Assignee: Hitachi Metals, Ltd.
    Inventors: Kumiko Konishi, Kiyoshi Oouchi, Keisuke Kobayashi, Akio Shima
  • Publication number: 20200303505
    Abstract: An n type semiconductor layer is formed over an n type semiconductor substrate made of silicon carbide, a p type impurity region is formed in the semiconductor layer, and an n type drain region and an n type source region are formed in the impurity region. A field insulating film having an opening that selectively opens a part of the impurity region located between the drain and source regions is formed over the impurity region and the drain and source regions. A gate insulating film is formed over the impurity region in the opening, and a gate electrode is formed on the gate insulating film. Here, a field relaxation layer having an impurity concentration higher than that of the impurity region is formed in at least a part of the impurity region located between the drain and source regions in plan view and located below the field insulating film.
    Type: Application
    Filed: November 4, 2019
    Publication date: September 24, 2020
    Applicant: Hitachi, Ltd.
    Inventors: Masahiro MASUNAGA, Shintaroh SATO, Akio SHIMA, Ryo KUWANA, Isao HARA
  • Patent number: 10692860
    Abstract: An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 23, 2020
    Assignee: HITACHI, LTD.
    Inventors: Ryuusei Fujita, Kumiko Konishi, Akio Shima
  • Publication number: 20200006066
    Abstract: In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.
    Type: Application
    Filed: January 30, 2018
    Publication date: January 2, 2020
    Inventors: Kumiko KONISHI, Kiyoshi OOUCHI, Keisuke KOBAYASHI, Akio SHIMA
  • Publication number: 20190326393
    Abstract: A MOSFET that has a drain region and a source region on an upper surface of a semiconductor substrate and a gate electrode that is formed on the semiconductor substrate, and an element separation insulating film that includes an opening portion which exposes an active region, on the semiconductor substrate, are formed. At this point, a gate leading-out interconnection that overlaps the element separation insulating film when viewed from above, and that is integrally combined with the gate electrode is formed in a position where the gate leading-out interconnection does not extend over a distance between both the drain region and the source region when viewed from above, on a region that is exposed from the gate electrode.
    Type: Application
    Filed: February 1, 2019
    Publication date: October 24, 2019
    Applicant: HITACHI, LTD.
    Inventors: Masahiro MASUNAGA, Akio SHIMA, Shintaroh SATO, Ryo KUWANA
  • Publication number: 20190319103
    Abstract: The purpose of the present invention is to provide a semiconductor device comprising an epitaxial layer formed on a SiC substrate, and a CMOS formed in the top part of the epitaxial layer, wherein growth of any defects present at the interface between the SiC substrate and the epitaxial layer is suppressed, and the reliability of the semiconductor device is improved. As a means to achieve the foregoing, a semiconductor device is formed such that the distance from a p-type diffusion layer to the interface between an n-type epitaxial layer and an n-type semiconductor substrate is larger than the thickness of a depletion layer that extends from the p-type diffusion layer to the back side of the n-type semiconductor substrate in response to the potential difference between a substrate electrode and another substrate electrode.
    Type: Application
    Filed: October 24, 2017
    Publication date: October 17, 2019
    Inventors: Masahiro MASUNAGA, Shintaroh SATO, Akio SHIMA, Digh HISAMOTO
  • Patent number: 10367090
    Abstract: Provided is a silicon carbide semiconductor device in which SiC-MOSFETs are formed within an active region of an n-type silicon carbide semiconductor substrate, and a p+-type semiconductor region is formed on an upper surface of an epitaxial layer so as to surround the active region.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 30, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Kumiko Konishi, Ryuusei Fujita, Kazuki Tani, Akio Shima
  • Publication number: 20190198495
    Abstract: An object of the present invention is to increase the reliability of a power module and a power converter and to extend their life. In order to achieve this, a power module includes: two switching devices each including a diode and a transistor, the two switching devices being electrically connected in parallel; and an insulating substrate on which the two switching devices are mounted. Further, a gate electrode of MOFET that each of the two switching device has is electrically connected to a gate resistance. Further, of the two switching devices, the gate resistance that is electrically connected to the switching device, whose current value is smaller when a predetermined voltage is applied in the forward direction of the body diode, is greater than the gate resistance that is electrically connected to the switching device whose current value is larger.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 27, 2019
    Inventors: Ryuusei FUJITA, Kumiko KONISHI, Akio SHIMA
  • Patent number: 10332997
    Abstract: There is provided a semiconductor device that improves reliability. The impurity concentrations of a p++ source region and a p++ drain region are 5×1020 cm?3 or more. The channel-region-side end portion of a first insulating film is disposed on a p+ source region. The end portion has an inclined surface where the first insulating film thickness is reduced from the p+ source region toward a channel region. The channel-region-side end portion of a second insulating film is disposed on a p+ drain region. The end portion has an inclined surface where the second insulating film thickness is reduced from the p+ drain region toward the channel region. A gate electrode is disposed on the channel region, the p+ source region, the p+ drain region, and the inclined surfaces of the first and the second insulating films through a gate insulating film including an aluminum oxide film.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: June 25, 2019
    Assignee: HITACHI, LTD.
    Inventors: Shintaroh Sato, Masahiro Masunaga, Akio Shima
  • Publication number: 20190148546
    Abstract: There is provided a semiconductor device that improves reliability. The impurity concentrations of a p|| source region and a p|| drain region are 5×1020 cm?3 or more. The channel-region-side end portion of a first insulating film is disposed on a p+ source region. The end portion has an inclined surface where the first insulating film thickness is reduced from the p? source region toward a channel region. The channel-region-side end portion of a second insulating film is disposed on a p+ drain region. The end portion has an inclined surface where the second insulating film thickness is reduced from the p+ drain region toward the channel region. A gate electrode is disposed on the channel region, the p+ source region, the p+ drain region, and the inclined surfaces of the first and the second insulating films through a gate insulating film including an aluminum oxide film.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 16, 2019
    Inventors: Shintaroh SATO, Masahiro MASUNAGA, Akio SHIMA
  • Publication number: 20190115465
    Abstract: Provided is a silicon carbide semiconductor device in which SiC-MOSFETs are formed within an active region of an n-type silicon carbide semiconductor substrate, and a p+-type semiconductor region is formed on an upper surface of an epitaxial layer so as to surround the active region.
    Type: Application
    Filed: July 2, 2018
    Publication date: April 18, 2019
    Applicant: HITACHI, LTD.
    Inventors: Kumiko KONISHI, Ryuusei FUJITA, Kazuki TANI, Akio SHIMA
  • Patent number: 10236370
    Abstract: An object of the present invention is to suppress energization deterioration due to crystal defects in a semiconductor device including SiC-MOSFET. To solve this problem, a semiconductor device of the present invention includes: an n?-type epitaxial layer formed on a main surface of an n+-type SiC substrate; a p-type termination region that is annularly formed in the n?-type epitaxial layer outside an active region; and an n-type hole annihilation region annularly formed in the n?-type epitaxial layer outside the p-type termination region, apart from the p-type termination region. Then, the n-type hole annihilation region has a first end surface facing the p-type termination region, as well as a second end surface on the opposite side of the first end surface.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: March 19, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Mori, Akio Shima
  • Publication number: 20180350973
    Abstract: An object of the present invention is to suppress energization deterioration due to crystal defects in a semiconductor device including SiC-MOSFET. To solve this problem, a semiconductor device of the present invention includes: an n?-type epitaxial layer formed on a main surface of an n+-type SiC substrate; a p-type termination region that is annularly formed in the n?-type epitaxial layer outside an active region; and an n-type hole annihilation region annularly formed in the n?-type epitaxial layer outside the p-type termination region, apart from the p-type termination region. Then, the n-type hole annihilation region has a first end surface facing the p-type termination region, as well as a second end surface on the opposite side of the first end surface.
    Type: Application
    Filed: September 15, 2015
    Publication date: December 6, 2018
    Applicant: Hitachi, Ltd.
    Inventors: Yuki MORI, Akio SHIMA
  • Patent number: 10115700
    Abstract: The object of the present invention is to compensate for a difference in threshold voltage between a plurality of switching devices incorporated in a power module. The present invention solves the subject described above by mounting a switching device having a high threshold voltage in comparison with a different switching device at a location at which the temperature of the power module during operation is higher than that at another location at which the different switching device is mounted. Eventually, a power conversion apparatus of a high performance and a vehicle drive apparatus of a high performance can be provided.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: October 30, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Ryuusei Fujita, Satoru Akiyama, Hiroshi Kageyama, Toru Masuda, Ayumu Hatanaka, Akio Shima
  • Publication number: 20180059263
    Abstract: There is provided a radiation detector using SiC and of a structure in which an electric field is applied to the interior of the entire SiC crystal constituting a radiation sensible layer, aiming to detect radiation while suppressing a reduction in electric signals generated in the radiation sensible layer.
    Type: Application
    Filed: July 6, 2015
    Publication date: March 1, 2018
    Inventors: Norifumi KAMESHIRO, Akio SHIMA