Abstract: A charge pump circuit includes a charge supplying capacitor, a constant voltage circuit such as a diode, and first and second switches serially arranged between a power supply terminal V.sub.DD and a ground terminal. When the first and second switches are turned ON, a voltage across the charge supplying capacitor is V.sub.DD -.DELTA. V, where .DELTA. V is a level shift amount produced by the constant voltage circuit. Also, the charge supplying capacitor is associated with third and fourth switches and they are serially arranged between the ground terminal and an output terminal. When the third and fourth switches are turned ON, the voltage across the charge supplying capacitor plus V.sub.DD, i.e., 2 V.sub.DD -.DELTA. V, is transferred to the output terminal.

Abstract: A semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a single chip, is manufactured by a silicon gate CMOS process. In order to reduce the number of repetitions of photolithographic process, low voltage N channel transistor domains and high voltage P channel transistor domains are simultaneously implanted by B ion, and low voltage P channel transistor domains and high voltage N channel transistor domains are simultaneously implanted by P ion.

Abstract: A crystal oscillation circuit has a constant-current load type inverter circuit receiving a regulated supply voltage from a voltage regulating circuit and functioning as an inverting amplifier for oscillation; a feedback circuit connected between an input and an output terminal of the inverter circuit and including a resistor and capacitors; and a crystal resonator connected between the input and output terminals of the inverter circuit. The inverter circuit is formed by a constant-current source and a P-channel type MOS-FET or an N-channel type MOS-FET. As the supply voltage from the voltage regulating circuit necessary as an oscillation starting voltage can be set at a low level, the current consumption of the overall oscillation circuit can be effectively reduced.

Abstract: An oscillation stoppage detecting circuit has a boost circuit to which is inputted an output of an oscillation circuit and a level detection circuit to which is inputted an output of the boost circuit. The boost circuit used here is, for example, a voltage doubler circuit which utilizes two diodes, a capacitor and an inverter, which is so-called a charge pump circuit. The boost circuit is operated by the oscillation output of the oscillation circuit and the oscillation stoppage is detected as a result of the comparison between the output voltage of the boost circuit and a threshold voltage of the level detection circuit. The arrangement enables to realize a circuit of low power consumption.

Abstract: A reference voltage generating circuit of the invention includes a differential amplifier having a pair of transistors of one conductivity type as differential input transistors; an operational amplifier having a pair of transistors of a conductivity type opposite to the one conductivity type as differential input transistors; and a feedback circuit constituted by a plurality of resistors, a first plurality of diodes connected in series and a second plurality of diodes connected in series. By the appropriate selection of the resistance value of each of the resistors, the temperature coefficient of the ouptut voltage can be made zero. The circuit of the invention does not require a start-up resistor which requires a considerably large chip area. The resultant reference voltage with respect to the ground potential or power supply potential outputted from the operational amplifier has no dependency on the variations or changes in the power supply voltage or in temperature.

Abstract: A semiconductor device includes an N-type semiconductor substrate, an N-channel type vertical MOSFET formed in the semiconductor substrate, a source electrode connected to a source region of the vertical MOSFET formed in the upper surface of the semiconductor substrate, a drain electrode of the vertical MOSFET formed on the bottom surface of the semiconductor substrate, a CMOS circuit formed in the upper surface of the semiconductor substrate to control the operation of the vertical MOSFET and a P-type diffused region formed between the vertical MOSFET and the CMOS circuit. The drain electrode is to be connected to a first power line, the source electrode being to be connected to a load connected to a second power line.