Abstract: A circuit device includes a drive circuit driving a resonator, an oscillation circuit having the resonator and a variable capacitance circuit coupled to an oscillation loop including the drive circuit, and a D/A converter circuit that performs D/A conversion on frequency control data and outputs a first voltage signal and a second voltage signal which are differential signals. The variable capacitance circuit includes a first variable capacitance capacitor, to one end of which the first voltage signal is input and, to the other end of which a first bias voltage is input and a second variable capacitance capacitor, to one end of which the second voltage signal is input and, to the other end of which a second bias voltage is input.

Abstract: A resonator device includes first and second resonators and an integrated circuit device. The integrated circuit device includes a first oscillation circuit configured to oscillate the first resonator, a second oscillation circuit configured to oscillate the second resonator, and a processing circuit configured to perform processing by using frequency difference information or frequency comparison information between a first clock signal generated by oscillating the first resonator and a second clock signal generated by oscillating the second resonator. The first resonator is supported on the integrated circuit device by a first support portion. The second resonator is supported on the integrated circuit device by a second support portion.

Abstract: An integrated circuit device includes: an AFE circuit (analog front-end circuit) that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; and a time-to-digital converter that receives the first signal from the AFE circuit via the first signal line, receives the second signal from the AFE circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value. At least one of the first signal line and the second signal line has redundant wiring for isometric wiring.

Abstract: A resonator device includes a first resonator that generates a reference clock signal, a second resonator that generates a first clock signal having a frequency adjusted based on the reference clock signal, and a circuit device that includes a temperature sensor for performing temperature compensation on an oscillation frequency of the first resonator. The temperature sensor is disposed on the circuit device such that the first resonator overlaps the temperature sensor in a plan view.

Abstract: A resonator device includes first and second resonators and an integrated circuit. The integrated circuit includes first and second oscillation circuits that oscillate first and second resonators, first and second terminals connected to the first oscillation circuit, and third and fourth terminals connected to the second oscillation circuit. The first terminal of the integrated circuit and one electrode of the first resonator are connected to each other via a bump. The third terminal and one electrode of the second resonator are connected to each other via a bump. In a plan view, at least a portion of the first resonator overlaps the first oscillation circuit and at least a portion of the second resonator overlaps the second oscillation circuit.

Abstract: An integrated circuit device includes a terminal region in which a second signal terminal to which a second signal is input is disposed, an AFE circuit (analog front-end circuit) that performs waveform shaping of the second signal, and a time-to-digital converter that converts a time difference between a transition timing of a first signal and a transition timing of the second signal subjected to waveform shaping, to a digital value. When a direction from a first side of the integrated circuit device toward a second side facing the first side is set as a first direction, the AFE circuit is disposed on the first direction side of the terminal region, and the time-to-digital converter is disposed on at least one side of the first direction side of the AFE circuit and a side of a direction intersecting the first direction.

Abstract: A circuit device includes a first circuit, a second circuit, and a comparator array section. The first circuit has a first DLL circuit having a plurality of delay elements, and delays a first signal. The second circuit has a second DLL circuit having a plurality of delay elements, and delays a second signal. The comparator array section has a plurality of phase comparators arranged in a matrix, the first delayed signal group from the first circuit and the second delayed signal group from the second circuit are input to the comparator array section, and the comparator array section outputs a digital signal corresponding to a time difference in the transition timing between the first signal and the second signal.

Abstract: A circuit device includes a drive circuit driving a resonator, an oscillation circuit having the resonator and a variable capacitance circuit coupled to an oscillation loop including the drive circuit, and a D/A converter circuit that performs D/A conversion on frequency control data and outputs a first voltage signal and a second voltage signal which are differential signals. The variable capacitance circuit includes a first variable capacitance capacitor, to one end of which the first voltage signal is input and, to the other end of which a first bias voltage is input and a second variable capacitance capacitor, to one end of which the second voltage signal is input and, to the other end of which a second bias voltage is input.

Abstract: A circuit device includes: a time-to-digital conversion circuit to which a first clock signal with a first clock frequency and a second clock signal with a second clock frequency different from the first clock frequency are input and that converts a time difference in transition timings of first and second signals into a digital value; and a synchronization circuit that synchronizes phases of the first and second clock signals. The time-to-digital conversion circuit calculates the digital value corresponding to the time difference by transitioning a signal level of the first signal based on the first clock signal after a phase synchronization timing of the first and second clock signals and compares the phase of the second clock signal to a phase of the second signal having a signal level is transitioned to correspond to the first signal.

Abstract: A circuit device includes a first PLL circuit to which a first clock signal having a first clock frequency generated using a first resonator and a reference clock signal are input, and which performs phase synchronization between the first clock signal and the reference clock signal, a second PLL circuit to which a second clock signal generated using a second resonator and having a second clock frequency different from the first clock frequency and the reference clock signal are input, and which performs phase synchronization between the second clock signal and the reference clock signal, and a time-to-digital conversion circuit adapted to convert time into a digital value using the first clock signal and the second clock signal.

Abstract: An integrated circuit device includes: a first oscillation circuit that oscillates a first resonator to generate a first clock signal with a first clock frequency; a second oscillation circuit that oscillates a second oscillation element to generate a second clock signal with a second clock frequency that is different from the first clock frequency; and a time-to-digital conversion circuit that converts a time into a digital value using the first and second clock signals.

Abstract: A circuit device includes a DLL circuit and an adjustment circuit. The DLL circuit has a plurality of delay elements, and a first clock signal generated using a first resonator and having a first clock frequency is input to the DLL circuit. Delayed clock signals from the delay elements of the DLL circuit, and a second clock signal generated using a second resonator and having a second clock frequency lower than the first clock frequency are input to the adjustment circuit, and the adjustment circuit adjusts delay amounts of the delay elements of the DLL circuit using a frequency difference between the first clock frequency and the second clock frequency.

Abstract: An integrated circuit device includes: an AFE circuit (analog front-end circuit) that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; and a time-to-digital converter that receives the first signal from the AFE circuit via the first signal line, receives the second signal from the AFE circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value. At least one of the first signal line and the second signal line has redundant wiring for isometric wiring.

Abstract: A circuit device includes an analog front-end circuit that receives a target signal is input, and a processing circuit that performs arithmetic processing based on an output signal from the analog front-end circuit. The analog front-end circuit includes a plurality of comparator circuits that compare the voltage level of the target signal to a plurality of threshold voltages and output a plurality of comparison result signals. The processing circuit obtains the transition timing of the target signal based on the comparison result signals and delayed-time information of the analog front-end circuit.

Abstract: A resonator device includes a first resonator that generates a reference clock signal, a second resonator that generates a first clock signal having a frequency adjusted based on the reference clock signal, and a circuit device that includes a temperature sensor for performing temperature compensation on an oscillation frequency of the first resonator. The temperature sensor is disposed on the circuit device such that the first resonator overlaps the temperature sensor in a plan view.

Abstract: An integrated circuit device includes a terminal region in which a second signal terminal to which a second signal is input is disposed, an AFE circuit (analog front-end circuit) that performs waveform shaping of the second signal, and a time-to-digital converter that converts a time difference between a transition timing of a first signal and a transition timing of the second signal subjected to waveform shaping, to a digital value. When a direction from a first side of the integrated circuit device toward a second side facing the first side is set as a first direction, the AFE circuit is disposed on the first direction side of the terminal region, and the time-to-digital converter is disposed on at least one side of the first direction side of the AFE circuit and a side of a direction intersecting the first direction.

Abstract: A resonator device includes first and second resonators and an integrated circuit device. The integrated circuit device includes a first oscillation circuit configured to oscillate the first resonator, a second oscillation circuit configured to oscillate the second resonator, and a processing circuit configured to perform processing by using frequency difference information or frequency comparison information between a first clock signal generated by oscillating the first resonator and a second clock signal generated by oscillating the second resonator. The first resonator is supported on the integrated circuit device by a first support portion. The second resonator is supported on the integrated circuit device by a second support portion.

Abstract: A resonator device includes first and second resonators and an integrated circuit. The integrated circuit includes first and second oscillation circuits that oscillate first and second resonators, first and second terminals connected to the first oscillation circuit, and third and fourth terminals connected to the second oscillation circuit. The first terminal of the integrated circuit and one electrode of the first resonator are connected to each other via a bump. The third terminal and one electrode of the second resonator are connected to each other via a bump. In a plan view, at least a portion of the first resonator overlaps the first oscillation circuit and at least a portion of the second resonator overlaps the second oscillation circuit.

Abstract: A circuit device includes a first PLL circuit to which a first clock signal having a first clock frequency generated using a first resonator and a reference clock signal are input, and which performs phase synchronization between the first clock signal and the reference clock signal, a second PLL circuit to which a second clock signal generated using a second resonator and having a second clock frequency different from the first clock frequency and the reference clock signal are input, and which performs phase synchronization between the second clock signal and the reference clock signal, and a time-to-digital conversion circuit adapted to convert time into a digital value using the first clock signal and the second clock signal.

Abstract: A circuit device includes a first circuit, a second circuit, and a comparator array section. The first circuit has a first DLL circuit having a plurality of delay elements, and delays a first signal. The second circuit has a second DLL circuit having a plurality of delay elements, and delays a second signal. The comparator array section has a plurality of phase comparators arranged in a matrix, the first delayed signal group from the first circuit and the second delayed signal group from the second circuit are input to the comparator array section, and the comparator array section outputs a digital signal corresponding to a time difference in the transition timing between the first signal and the second signal.