Patents by Inventor Akio TSUTSUMI

Akio TSUTSUMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180091158
    Abstract: A circuit device includes: a time-to-digital conversion circuit to which a first clock signal with a first clock frequency and a second clock signal with a second clock frequency different from the first clock frequency are input and that converts a time difference in transition timings of first and second signals into a digital value; and a synchronization circuit that synchronizes phases of the first and second clock signals. The time-to-digital conversion circuit calculates the digital value corresponding to the time difference by transitioning a signal level of the first signal based on the first clock signal after a phase synchronization timing of the first and second clock signals and compares the phase of the second clock signal to a phase of the second signal having a signal level is transitioned to correspond to the first signal.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 29, 2018
    Inventors: Yasuhiro SUDO, Katsuhiko MAKI, Hideo HANEDA, Akio TSUTSUMI, Takashi KURASHINA
  • Publication number: 20180088160
    Abstract: A physical quantity measurement apparatus includes a first resonator, a second oscillator, and an integrated circuit device. The integrated circuit device includes a first oscillation circuit that causes the first resonator to oscillate, and thus generate a first clock signal having a first clock frequency, a second oscillation circuit that causes the second oscillator to oscillate, and thus generate a second clock signal having a second clock frequency which is different from the first clock frequency, and a measurement unit that is provided with a time-to-digital conversion circuit which converts time into a digital value by using the first clock signal and the second clock signal.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 29, 2018
    Inventors: Katsuhiko MAKI, Hideo HANEDA, Takashi KURASHINA, Akio TSUTSUMI, Yasuhiro SUDO
  • Publication number: 20180091156
    Abstract: An integrated circuit device includes: a first oscillation circuit that oscillates a first resonator to generate a first clock signal with a first clock frequency; a second oscillation circuit that oscillates a second oscillation element to generate a second clock signal with a second clock frequency that is different from the first clock frequency; and a time-to-digital conversion circuit that converts a time into a digital value using the first and second clock signals.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 29, 2018
    Inventors: Katsuhiko MAKI, Hideo HANEDA, Takashi KURASHINA, Akio TSUTSUMI, Yasuhiro SUDO
  • Publication number: 20180091159
    Abstract: A circuit device includes a DLL circuit and an adjustment circuit. The DLL circuit has a plurality of delay elements, and a first clock signal generated using a first resonator and having a first clock frequency is input to the DLL circuit. Delayed clock signals from the delay elements of the DLL circuit, and a second clock signal generated using a second resonator and having a second clock frequency lower than the first clock frequency are input to the adjustment circuit, and the adjustment circuit adjusts delay amounts of the delay elements of the DLL circuit using a frequency difference between the first clock frequency and the second clock frequency.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 29, 2018
    Inventors: Akio TSUTSUMI, Katsuhiko MAKI
  • Patent number: 9658065
    Abstract: A detection circuit (physical quantity detection circuit) includes a digital arithmetic operation circuit (arithmetic operation processing portion) that performs an arithmetic operation process of generating an arithmetic operation signal according to a magnitude of a physical quantity, on the basis of a detection signal corresponding to the physical quantity. The digital arithmetic operation circuit performs an arithmetic operation process including a power supply voltage fluctuation correction process of correcting at least one of the detection signal and a signal which is obtained by a portion of the arithmetic operation process with respect to the detection signal, on the basis of a correction expression using a power supply voltage to be supplied as a variable.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: May 23, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Akio Tsutsumi
  • Publication number: 20140318244
    Abstract: A detection circuit (physical quantity detection circuit) includes a digital arithmetic operation circuit (arithmetic operation processing portion) that performs an arithmetic operation process of generating an arithmetic operation signal according to a magnitude of a physical quantity, on the basis of a detection signal corresponding to the physical quantity. The digital arithmetic operation circuit performs an arithmetic operation process including a power supply voltage fluctuation correction process of correcting at least one of the detection signal and a signal which is obtained by a portion of the arithmetic operation process with respect to the detection signal, on the basis of a correction expression using a power supply voltage to be supplied as a variable.
    Type: Application
    Filed: April 23, 2014
    Publication date: October 30, 2014
    Applicant: Seiko Epson Corporation
    Inventor: Akio TSUTSUMI