Patents by Inventor Akio Wakejima
Akio Wakejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180233590Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: ApplicationFiled: March 16, 2018Publication date: August 16, 2018Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Patent number: 9954087Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: GrantFiled: August 27, 2014Date of Patent: April 24, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Publication number: 20140367743Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: ApplicationFiled: August 27, 2014Publication date: December 18, 2014Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Patent number: 8853666Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: GrantFiled: October 25, 2006Date of Patent: October 7, 2014Assignee: Renesas Electronics CorporationInventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Patent number: 8476756Abstract: A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K1yy?K1xx>K1zz, where directional components of a three-dimensional thermal conductivity of the heat sink section in X, Y, and Z directions are determined as Kxx, Kyy, and Kzz. A relation among directional components of a thermal conductivity of the second heat sink section is K2zz?K2yy>K2xx or K2yy?K2zz>K2xx, where the directional components of the thermal conductivity of the second heat sink section in X, Y, and X directions are determined as K2xx, K2yy, and K2zz.Type: GrantFiled: September 21, 2011Date of Patent: July 2, 2013Assignee: NEC CorporationInventors: Naotaka Kuroda, Akio Wakejima, Masahiro Tanomura, Hironobu Miyamoto
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Patent number: 8476980Abstract: A power amplifier includes an amplifying circuit, and first through third transmission lines. The amplifying circuit amplifies an input signal having a fundamental frequency to generate a first amplified signal and a second amplified signal whose phase is opposed to the first amplified signal. The first transmission line adds a first group of phases, different in correspondence with a frequency, to the first amplified signal by using a left-handed material to generate a first transmission signal. The second transmission line adds a second group of phases, different in correspondence with a frequency, to the second amplified signal by using a right-handed material to generate a second transmission signal. The third transmission line overlaps the first and the second transmission signals to generate an output signal. The first and the second group of phases include a phase difference configured to weaken a second harmonic and a third harmonic.Type: GrantFiled: February 3, 2010Date of Patent: July 2, 2013Assignee: NEC CorporationInventor: Akio Wakejima
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Patent number: 8466495Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of said carrier supply layer, t denotes a thickness of said p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.Type: GrantFiled: May 10, 2012Date of Patent: June 18, 2013Assignee: NEC CorporationInventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Yasuhiro Murase, Kazuki Ota, Akio Wakejima, Naotaka Kuroda
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Publication number: 20120217547Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of said carrier supply layer, t denotes a thickness of said p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.Type: ApplicationFiled: May 10, 2012Publication date: August 30, 2012Applicant: NEC CORPORATIONInventors: Yuji ANDO, Hironobu MIYAMOTO, Tatsuo NAKAYAMA, Yasuhiro OKAMOTO, Takashi INOUE, Yasuhiro MURASE, Kazuki OTA, Akio WAKEJIMA, Naotaka KURODA
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Publication number: 20120188010Abstract: A power amplifier includes an amplifying circuit, and first through third transmission lines. The amplifying circuit amplifies an input signal having a fundamental frequency to generate a first amplified signal and a second amplified signal whose phase is opposed to the first amplified signal. The first transmission line adds a first group of phases, different in correspondence with a frequency, to the first amplified signal by using a left-handed material to generate a first transmission signal. The second transmission line adds a second group of phases, different in correspondence with a frequency, to the second amplified signal by using a right-handed material to generate a second transmission signal. The third transmission line overlaps the first and the second transmission signals to generate an output signal. The first and the second group of phases include a phase difference configured to weaken a second harmonic and a third harmonic.Type: ApplicationFiled: February 3, 2010Publication date: July 26, 2012Applicant: NEC CORPORATIONInventor: Akio Wakejima
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Patent number: 8198652Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of the carrier supply layer, t denotes a thickness of the p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.Type: GrantFiled: March 29, 2007Date of Patent: June 12, 2012Assignee: NEC CorporationInventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Yasuhiro Murase, Kazuki Ota, Akio Wakejima, Naotaka Kuroda
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Publication number: 20120012995Abstract: A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K1yy?K1xx>K1zz, where directional components of a three-dimensional thermal conductivity of the heat sink section in X, Y, and Z directions are determined as Kxx, Kyy, and Kzz. A relation among directional components of a thermal conductivity of the second heat sink section is K2zz?K2yy>K2xx or K2yy?K2zz>K2xx, where the directional components of the thermal conductivity of the second heat sink section in X, Y, and X directions are determined as K2xx, K2yy, and K2zz.Type: ApplicationFiled: September 21, 2011Publication date: January 19, 2012Applicant: NEC CORPORATIONInventors: Naotaka Kuroda, Akio Wakejima, Masahiro Tanomura, Hironobu Miyamoto
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Patent number: 8063484Abstract: A semiconductor device, comprising: a semiconductor element 20 having a rectangular two-dimensional geometry and serving as a heat source; and a heat sink section 25 having the semiconductor element 20 mounted thereon, wherein a relation among the directional components of said thermal conductivity is: Kzz?Kyy>Kxx, where directional components of three-dimensional thermal conductivity of the heat sink section 25 in X, Y and Z directions are determined as Kxx, Kyy and Kzz, and where the longer side direction of the semiconductor element 20 is defined as X direction, the shorter side direction thereof is defined as Y direction and the thickness direction is defined as Z direction.Type: GrantFiled: October 25, 2007Date of Patent: November 22, 2011Assignee: NEC CorporationInventors: Naotaka Kuroda, Akio Wakejima, Masahiro Tanomura, Hironobu Miyamoto
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Patent number: 7863648Abstract: A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode (118) overlap the upper part of a structure including the first field plate electrode and a gate electrode (113) is designated as Lol, and the gate length is Lg, the relation expressed as 0 ?Lol/Lg?1 holds.Type: GrantFiled: June 12, 2006Date of Patent: January 4, 2011Assignee: NEC CorporationInventors: Hironobu Miyamoto, Yuji Ando, Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota, Akio Wakejima, Kensuke Kasahara, Yasuhiro Murase, Kohji Matsunaga, Katsumi Yamanoguchi, Hidenori Shimawaki
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Patent number: 7800131Abstract: A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0?Lol/Lg?1 holds.Type: GrantFiled: June 12, 2006Date of Patent: September 21, 2010Assignee: NEC CorporationInventors: Hironobu Miyamoto, Yuji Ando, Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota, Akio Wakejima, Kensuke Kasahara, Yasuhiro Murase, Kohji Matsunaga, Katsumi Yamanoguchi, Hidenori Shimawaki
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Publication number: 20100224910Abstract: Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0?y?1); a carrier supply layer 13 composed of AlxGa1-xN (0?x?1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x<NA×?×t [cm?2]<5.6×1013x, where x denotes an Al compositional ratio of the carrier supply layer, t denotes a thickness of the p-type layer, NA denotes an impurity concentration, and ? denotes an activation ratio.Type: ApplicationFiled: March 29, 2007Publication date: September 9, 2010Applicant: NEC CorporationInventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Yasuhiro Murase, Kazuki Ota, Akio Wakejima, Naotaka Kuroda
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Publication number: 20100007013Abstract: A semiconductor device, comprising: a semiconductor element 20 having a rectangular two-dimensional geometry and serving as a heat source; and a heat sink section 25 having the semiconductor element 20 mounted thereon, wherein a relation among the directional components of said thermal conductivity is: Kzz?Kyy>Kxx, where directional components of three-dimensional thermal conductivity of the heat sink section 25 in X, Y and Z directions are determined as Kxx, Kyy and Kzz, and where the longer side direction of the semiconductor element 20 is defined as X direction, the shorter side direction thereof is defined as Y direction and the thickness direction is defined as Z direction.Type: ApplicationFiled: October 25, 2007Publication date: January 14, 2010Inventors: Naotaka Kuroda, Akio Wakejima, Masahiro Tanomura, Hironobu Miyamoto
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Publication number: 20090230429Abstract: A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode (118) overlap the upper part of a structure including the first field plate electrode and a gate electrode (113) is designated as Lol, and the gate length is Lg, the relation expressed as 0?Lol/Lg?1 holds.Type: ApplicationFiled: June 12, 2006Publication date: September 17, 2009Applicant: NEC CORPORATIONInventors: Hironobu Miyamoto, Yuji Ando, Yasuhiro Okamoto, Tasuo Nakayama, Takashi Inoue, Kazuki Ota, Akio Wakejima, Kensuke Kasahara, Yasuhiro Murase, Kohji Matsunaga, Katsumi Yamanoguchi, Hidenori Shimawaki
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Publication number: 20090173968Abstract: A semiconductor device 100 contains an undoped GaN channel layer 105, an AlGaN electron donor layer 106 provided on the undoped GaN channel layer 105 as being brought into contact therewith, an undoped GaN layer 107 provided on the AlGaN electron donor layer 106, a source electrode 101 and a drain electrode 103 provided on the undoped GaN layer 107 as being spaced from each other, a recess 111 provided in the region between the source electrode 101 and the drain electrode 103, as being extended through the undoped GaN layer 107, a gate electrode 102 buried in the recess 111 as being brought into contact with the AlGaN electron donor layer 106 on the bottom surface thereof, and an SiN film 108 provided on the undoped GaN layer 107, in the region between the gate electrode 102 and the drain electrode 103.Type: ApplicationFiled: December 12, 2006Publication date: July 9, 2009Applicant: NEC CORPORATIONInventors: Kouji Matsunaga, Kazuki Ota, Yasuhiro Okamoto, Tatsuo Nakayama, Akio Wakejima, Yuji Ando, Hironobu Miyamoto, Takashi Inoue, Yasuhiro Murase
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Publication number: 20090045438Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: ApplicationFiled: October 25, 2006Publication date: February 19, 2009Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Publication number: 20020171096Abstract: In a field effect transistor, there are provided a gate electrode on a Schottky layer over an InP channel layer over the substrate, and a field control electrode extending over an insulating layer and separated from the Schottky layer and being positioned between the gate electrode and the drain electrode for controlling an expansion of a space charge region in the channel layer.Type: ApplicationFiled: May 17, 2002Publication date: November 21, 2002Applicant: NEC CORPORATIONInventors: Akio Wakejima, Kazuki Ota, Kohji Matsunaga, Walter Contrata, Masaaki Kuzuhara