Patents by Inventor Akira Fujimura

Akira Fujimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140223393
    Abstract: A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the reticle is an OPC-corrected version of an input pattern, and where the sensitivity of the pattern on the reticle to manufacturing variation is reduced. A method for fracturing or mask data preparation is also disclosed.
    Type: Application
    Filed: December 13, 2013
    Publication date: August 7, 2014
    Applicant: D2S, Inc.
    Inventors: Akira Fujimura, Kazuyuki Hagiwara, Stephen F. Meier, Ingo Bork
  • Patent number: 8771906
    Abstract: In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, in which the union of shots from one of a plurality of exposure passes is different than the union of shots from a different exposure pass. Methods for manufacturing a reticle and manufacturing an integrated circuit are also disclosed, in which the union of shots from one of a plurality of charged particle beam exposure passes is different than the union of shots from a different exposure pass.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: July 8, 2014
    Assignee: D2S, Inc.
    Inventors: Harold Robert Zable, Akira Fujimura
  • Publication number: 20140158916
    Abstract: A method and system for fracturing or mask data preparation is disclosed in which a desired substrate pattern for a substrate is input. A plurality of charged particle beam shots is then determined which will form a reticle pattern on a reticle, where the reticle pattern will produce a substrate pattern on the substrate using an optical lithography process, wherein the substrate pattern is within a predetermined tolerance of the desired substrate pattern. A similar method and a similar system for forming a pattern on a reticle are also disclosed.
    Type: Application
    Filed: February 11, 2014
    Publication date: June 12, 2014
    Applicant: D2S, Inc.
    Inventor: Akira Fujimura
  • Publication number: 20140162466
    Abstract: A method and system for fracturing or mask data preparation is disclosed in which a plurality of charged particle beam shots is determined which will produce a pattern on a reticle, where the reticle is to be used to form an aerial image on a resist-coated substrate using an optical lithographic process. A simulated reticle pattern is then calculated from the plurality of charged particle beam shots. A calculated aerial substrate image is then calculated using the simulated reticle pattern, and a shot in the plurality of shots is modified to improve the calculated aerial substrate image. Similar methods for forming a pattern on a reticle and for manufacturing an integrated circuit are also disclosed.
    Type: Application
    Filed: February 11, 2014
    Publication date: June 12, 2014
    Applicant: D2S, INC.
    Inventor: Akira Fujimura
  • Patent number: 8745874
    Abstract: A method of manufacturing a wheel support bearing assembly having a plastically deformed portion engageable with an inclined surface portion of an annular stepped area in the inner race segment. The method includes that the plastically deformed portion, which is of a cylindrical configuration before it is deformed, is formed by pressing a crimping punch, of which front end portion outer peripheral surface is a tapered shape, axially into an inner peripheral surface of the inboard end portion of the hub axle to allow the cylindrical plastically deformed portion to be crimped in the diameter expanded condition.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: June 10, 2014
    Assignee: NTN Corporation
    Inventors: Kazunori Kubota, Kazuo Komori, Hiroshi Matsunaga, Akira Fujimura, Tetsuya Hashimoto, Masahiro Kiuchi
  • Patent number: 8745549
    Abstract: A method for fracturing or mask data preparation or proximity effect correction or optical proximity correction or mask process correction is disclosed in which a set of charged particle beam shots is determined that is capable of forming a pattern on a surface, wherein critical dimension (CD) split is reduced through the use of overlapping shots.
    Type: Grant
    Filed: February 5, 2012
    Date of Patent: June 3, 2014
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Robert C. Pack
  • Patent number: 8745555
    Abstract: Methods for designing and manufacturing an integrated circuit are disclosed, in which the physical design process for a standard cell or cells utilizes a preferred diagonal direction for minimum-width patterns on at least one layer, where the standard cell or cells are used in the layout of an integrated circuit. The methods also include forming the patterns on a photomask using model-based fracturing techniques with charged particle beam simulation, and forming the patterns on a substrate such a silicon wafer using the photomask and an optical lithographic process with directional illumination which is optimized for the preferred diagonal direction.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: June 3, 2014
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Larry Lam Chau, Tam Dinh Thanh Nguyen
  • Publication number: 20140146298
    Abstract: A device for charged particle beam lithography is disclosed which includes an inputting device, a character projection stencil and a reducing lens. The inputting device reads a set of shots, where each shot has a magnification. The character projection stencil contains a character pattern. The reducing lens introduces magnification variation of the stencil character pattern when writing the pattern onto a surface, where the magnification of the reducing lens can be varied from shot to shot.
    Type: Application
    Filed: March 22, 2013
    Publication date: May 29, 2014
    Inventor: Akira Fujimura
  • Publication number: 20140134523
    Abstract: A method for forming patterns on a surface using charged particle beam lithography is disclosed, in which a stencil is provided comprising first and second apertures, where circular or nearly-circular patterns in a first plurality of sizes are formed on the surface using the first aperture by varying shot dosage, and where circular or nearly-circular patterns in a second plurality of sizes are formed on the surface using the second aperture by varying shot dosage. A similar method for fracturing or mask data preparation is also disclosed. A stencil for charged particle beam lithography is also disclosed, where the stencil comprises first aperture and second apertures capable of forming, in one shot, patterns in a first and a second range of sizes on a surface by varying the shot dosage, where the first range of sizes is discontinuous with the second range of sizes.
    Type: Application
    Filed: December 16, 2013
    Publication date: May 15, 2014
    Applicant: D2S, INC.
    Inventors: Akira Fujimura, Michael Tucker
  • Publication number: 20140129996
    Abstract: A method for mask process correction or forming a pattern on a resist-coated reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle, and where the pattern exposure information is modified to lower the calculated sensitivity. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a resist-coated reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 8, 2014
    Applicant: D2S, INC.
    Inventors: Akira Fujimura, Kazuyuki Hagiwara, Robert C. Pack, Anatoly Aadamov
  • Publication number: 20140129997
    Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 8, 2014
    Applicant: D2S, INC.
    Inventors: Akira Fujimura, Kazuyuki Hagiwara, Robert C. Pack
  • Publication number: 20140127628
    Abstract: A method for forming a pattern on a surface using charged particle beam lithography is disclosed, where the shots in an ordered set of input shots are modified within a subfield to reduce either a thermal variation or a maximum temperature of the surface during exposure by the charged particle beam writer. A method for fracturing or mask data processing is also disclosed, where an ordered set of shots is generated which will expose at least one subfield of a surface using a shaped beam charged particle beam writer, and where a temperature or a thermal variation generated on the surface during the exposure of one subfield is calculated. Additionally, a method for forming a pattern on a surface with an ordered set of shots using charged particle beam lithography is disclosed, in which a blanking period following a shot is lengthened to reduce the maximum temperature of the surface.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 8, 2014
    Applicant: D2S, Inc.
    Inventors: Akira Fujimura, Ryan Pearman, Anatoly Aadamov
  • Patent number: 8719739
    Abstract: A method for mask data preparation (MDP) is disclosed, in which a set of shots is determined that will form a pattern on a reticle, where the determination includes calculating the pattern that will be formed on a substrate using an optical lithographic process with a reticle formed using the set of shots. A method for optical proximity correction (OPC) or MDP is also disclosed, in which a preliminary set of charged particle beam shots is generated using a preliminary mask model, and then the shots are modified by calculating both a reticle pattern using a final mask model, and a resulting substrate pattern. A method for OPC is also disclosed, in which an ideal pattern for a photomask is calculated from a desired substrate pattern, where the model used in the calculation includes only optical lithography effects and/or substrate processing effects.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: May 6, 2014
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Anatoly Aadamov, Eldar Khaliullin, Ingo Bork
  • Patent number: 8713484
    Abstract: Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit (“IC”). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: April 29, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Louis K. Scheffer, Akira Fujimura
  • Patent number: 8703389
    Abstract: In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (?f). At least some shots in the plurality of shots overlap other shots. In some embodiments, ?f is reduced by controlling the amount of shot overlap in the plurality of shots, either during initial shot determination, or in a post-processing step. The reduced sensitivity to ?f expands the process window for the charged particle beam lithography process.
    Type: Grant
    Filed: June 25, 2011
    Date of Patent: April 22, 2014
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Ingo Bork
  • Patent number: 8677860
    Abstract: A transmission is provided in which gears (31 to 34) of a first gear group provided on a first auxiliary input shaft (13) to which driving force of a main input shaft (12) is transmitted via a first clutch (24) and gears (37 to 39) of a second gear group provided on a second auxiliary input shaft (14) to which the driving force of the main input shaft (12) is transmitted via an idle gear (17 to 19) and a second clutch (25) use in common gears (43 to 46) of a third gear group provided on an output shaft (16), whereby it becomes possible to cut the number of components and reduce the dimensions of the transmission.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: March 25, 2014
    Assignee: Honda Motor Co., Ltd
    Inventors: Hisato Nishida, Kazuma Hatakeyama, Akira Fujimura, Shuichi Fujimoto
  • Patent number: 8671378
    Abstract: The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: March 11, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Raghu Chalasani, Akira Fujimura
  • Patent number: 8669023
    Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. A method for forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: March 11, 2014
    Assignee: D2S, Inc.
    Inventor: Akira Fujimura
  • Patent number: 8637211
    Abstract: A method for manufacturing a semiconductor device is disclosed, wherein during the physical design process, a curvilinear path is designed to represent an interconnecting wire on the fabricated semiconductor device. A method for fracturing or mask data preparation (MDP) is also disclosed in which a manhattan path which is part of the physical design of an integrated circuit is modified to create a curvilinear pattern, and where a set of charged particle beam shots is generated, where the set of shots is capable of forming the curvilinear pattern on a resist-coated surface.
    Type: Grant
    Filed: October 9, 2011
    Date of Patent: January 28, 2014
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Michael Tucker
  • Publication number: 20130337372
    Abstract: A surface manufactured using variable shaped beam (VSB) shots is disclosed, where either: 1) the left edge of a first VSB shot intersects the top edge of a second VSB shot, and the bottom edge of the first VSB shot intersects the right edge of the second VSB shot; or 2) the left edge of the first VSB shot intersects the bottom edge of a second VSB shot, and the top edge of the first VSB shot intersects the right edge of the second VSB shot; and where neither shot crosses a field boundary of the VSB charged particle beam writer.
    Type: Application
    Filed: August 19, 2013
    Publication date: December 19, 2013
    Applicant: D2S, INC.
    Inventors: Akira Fujimura, Lance A. Glasser