Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: This invention provides a solid-state imaging device which enables its cell area to be reduced while maintaining a light receiving area. First, a plurality of isolation areas are formed in a semiconductor substrate. Then, p-type well is formed by implanting p-type impurity into the interior organization of an active area surrounded by the isolation areas. Next, by using ion implantation method, a charge accumulating area, which is a n-type semiconductor area, is formed deep in the p-type well. Consequently, photo diode is formed in a deep portion apart from the surface of the semiconductor substrate. After that, an electric transferring MIS transistor is formed above and apart from the charge accumulating area, so that the photo diode and the MIS transistor are formed in a vertical structure.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes;of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacitor. The capacitor is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using a structure with decreased resistance such as silicided structure. In addition, there are made common the processing for lowering the resistance of the gate electrode of the transfer MISFETs and the processing for forming the local wiring lines.

Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

Abstract: To eliminate misfit dislocation occurring in a hetero-interface and to provide a bipolar transistor capable of a high speed operation, the bipolar transistor is configured such that the energy band gap is progressively narrowing from part of an emitter layer towards part of a collector layer through a base layer.

Abstract: A suspension control system for controlling a suspension having a shock absorber provided for each wheel of a vehicle includes a damping force change rate detector which detects a damping force change rate indicating a rate of change of a damping force of the shock absorber, and a damping force controller which alters the setting of the damping force on the basis of a relationship between the damping force change rate and an adjustment reference value. The system also includes a road surface condition detector which detects a condition of a road surface on which the vehicle is running on the basis of a change of the damping force of the shock absorber. Further, the system includes a damping force adjustment correcting unit which corrects the adjustment reference value by learning the adjustment reference value on the basis of a parameter related to the damping force of the shock absorber which reflects the condition of the road surface.

Abstract: A suspension control system for controlling a suspension having a shock absorber provided for a wheel of a vehicle includes a damping force detector which generates a damping force detection signal which indicates a change of a damping force of the shock absorber based on a condition of a road surface on which the vehicle is running. The system also includes a sprung resonance component extraction unit which extracts a sprung resonance component signal from the damping force detection signal. The sprung resonance component signal includes components having frequencies around a sprung resonance frequency of the shock absorber. Further, the system includes a determining part which determines whether or not the sprung resonance component signal exceeds a first level range provided for detecting a sign of the occurrence of a long-term vehicle vibration and which outputs a determination result.

Abstract: A suspension control system for controlling a suspension having a shock absorber provided for a wheel of a vehicle includes a damping force change rate detector which detects a damping force change rate indicating a rate of change of a damping force of the shock absorber, and a damping force controller which alters the setting of the damping force on the basis of the relationship between the damping force change rate and an adjustment reference value. The system also includes a road surface condition detector which detects, for every first period, the condition of a road surface on which the vehicle is running on the basis of a change of the damping force of the shock absorber, and a damping force adjustment correcting unit which corrects the adjustment reference value by learning, for every second period, the adjustment reference value on the basis of a parameter related to the damping force of the shock absorber which reflects the condition of the road surface.

Abstract: A shock absorber control system having shock absorbers provided respectively between wheels of a vehicle and a body thereof includes road surface condition detecting units provided for the respective shock absorbers, and damping force characteristic alteration units provided for the respective shock absorbers. The shock absorber control system also includes a correction unit for separately generating signals indicative of detection characteristics of the road surface condition detecting units provided for the respective shock absorbers on the basis of road surface condition detection signals generated by the road surface condition detecting units and for separately correcting either reference values used for determining whether or not the road surface is rough by the damping force characteristic alteration units or the road surface condition detection signals on the basis of the detection characteristics of the road surface condition detecting units provided for the respective shock absorbers.

Abstract: A suspension control system controls suspensions provided for wheels of a vehicle includes a driving condition detecting part for detecting a driving condition of the vehicle, and a determination part for determining whether or not the driving condition detected by the driving condition detecting part coincides with a predetermined driving condition. The suspensions are grouped into a plurality of groups. Also the system includes a control part for separately controlling the suspensions on the basis of the driving condition when the determination part determines that the driving condition does not coincide with the predetermined driving condition and for controlling the suspensions for each of the groups so that the suspensions in an identical group are set to an identical condition when the determination part determines that the driving condition coincides with the predetermined driving condition.

Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

Abstract: An MOSFET provided with a gate insulating film formed on a semiconductor surface between a source region and a drain region, a gate electrode formed on the gate insulating film, and a channel region sandwiched between the source region and the drain region and made up of a first layer and a second layer is disclosed in which the first layer lies beneath the gate insulating film and is opposite in conductivity type to the source and drain regions, the second layer lies beneath the first layer and has the same conductivity type as the source and drain regions, and the length of the second layer between the source region and the drain region is greater than the length of the first layer between the source region and the drain region.