Patents by Inventor Akira Goda

Akira Goda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12266407
    Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: April 1, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee, David Scott Ebsen, Dung Viet Nguyen, Akira Goda
  • Publication number: 20250087275
    Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. A first string of the plurality of strings can comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block: apply a voltage having a first value to a sense line coupled to the plurality of strings; apply a voltage having a second value less than the first value to the first group of access lines; and apply a voltage having a third value less than the second value to the second group of access lines.
    Type: Application
    Filed: July 10, 2024
    Publication date: March 13, 2025
    Inventors: Shyam Sunder Raghunathan, Yingda Dong, Akira Goda
  • Patent number: 12249364
    Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: March 11, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Huai-Yuan Tseng, Akira Goda, Kishore Kumar Muchherla, James Fitzpatrick, Tomoharu Tanaka, Eric N. Lee, Dung V. Nguyen, David Ebsen
  • Publication number: 20250077415
    Abstract: An apparatus can comprise a memory array comprising a plurality of erase blocks and a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller coupled to the memory array can be configured to: receive a write command corresponding to data to be written to the memory array; determine a temperature classification for the data to which the write command corresponds; and, based on the determined temperature classification for the data, route the data to a first write cursor or to one of a number of different write cursors.
    Type: Application
    Filed: July 12, 2024
    Publication date: March 6, 2025
    Inventors: Kishore K. Muchherla, Hong Lu, Mark Ish, Akira Goda
  • Publication number: 20250078932
    Abstract: A system includes a memory device including a memory array and processing logic, operatively coupled with the memory array, to perform operations including identifying a set of cells of the memory array to be programmed with dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 6, 2025
    Inventors: Jeffrey S. McNeil, Kishore Kumar Muchherla, Sead Zildzic, Akira Goda, Jonathan S. Parry, Violante Moschiano
  • Publication number: 20250077416
    Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.
    Type: Application
    Filed: July 23, 2024
    Publication date: March 6, 2025
    Inventors: Huai-Yuan Tseng, Xiangyu Tang, Eric N. Lee, Haibo Li, Kishore Kumar Muchherla, Akira Goda
  • Publication number: 20250053301
    Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Jeffrey S. McNeil, Jonathan S. Parry, Ugo Russo, Akira Goda, Kishore Kumar Muchherla, Violante Moschiano, Niccolo' Righetti, Silvia Beltrami
  • Patent number: 12217799
    Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Paing Z. Htet, Akira Goda, Eric N. Lee, Jeffrey S. McNeil, Junwyn A. Lacsao, Kishore Kumar Muchherla, Sead Zildzic, Violante Moschiano
  • Patent number: 12219772
    Abstract: Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: February 4, 2025
    Inventors: Akira Goda, Haitao Liu, Jin Chen, Guangyu Huang, Mojtaba Asadirad
  • Patent number: 12216915
    Abstract: Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Animesh R. Chowdhury, Kishore K. Muchherla, Nicola Ciocchini, Akira Goda, Jung Sheng Hoei, Niccolo′ Righetti, Jonathan S. Parry
  • Publication number: 20250022962
    Abstract: An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 16, 2025
    Inventors: Akira Goda, Marc Aoulaiche
  • Patent number: 12199070
    Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: January 14, 2025
    Assignee: Lodestar Licensing Group LLC
    Inventors: Kunal R. Parekh, Paolo Tessariol, Akira Goda
  • Patent number: 12200938
    Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.
    Type: Grant
    Filed: October 30, 2023
    Date of Patent: January 14, 2025
    Inventors: Haitao Liu, Kamal M. Karda, Gurtej S. Sandhu, Sanh D. Tang, Akira Goda, Lifang Xu
  • Publication number: 20250014655
    Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.
    Type: Application
    Filed: September 24, 2024
    Publication date: January 9, 2025
    Inventors: Nicola Ciocchini, Animesh R. Chowdhury, Kishore Kumar Muchherla, Akira Goda, Jung Sheng Hoei, Niccolo' Righetti, Jonathan S. Parry
  • Publication number: 20250013382
    Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
    Type: Application
    Filed: September 24, 2024
    Publication date: January 9, 2025
    Inventors: Kishore Kumar Muchherla, Dung V. Nguyen, Dave Scott Ebsen, Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Akira Goda, Eric N. Lee
  • Publication number: 20250006275
    Abstract: An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. Control circuitry can be configured to: receive a command corresponding to a sensing operation to be performed on a selected access line of a first group of access lines corresponding to a first erase block; and determine an adjusted sense voltage to be applied to the selected access line in association with performing the sensing operation. The adjusted sense voltage is based on: a quantity of the first group of access lines that are programmed; or a quantity of the second group of access lines that are programmed; or both.
    Type: Application
    Filed: June 20, 2024
    Publication date: January 2, 2025
    Inventors: Shyam Sunder Raghunathan, Akira Goda, Kishore K. Muchherla
  • Publication number: 20240419544
    Abstract: A memory device to use added known data as part of data written to memory cells with redundant data generated according to an error correction code (ECC). The code rate of the ECC may limit its capability to recover from excessive errors in the stored data. To reduce the errors, the added data retrieved from the memory cells can be corrected without using the ECC. Subsequently, remaining errors can be corrected via the ECC. Optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. Different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.
    Type: Application
    Filed: August 30, 2024
    Publication date: December 19, 2024
    Inventors: Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Akira Goda, Mustafa N. Kaynak
  • Publication number: 20240420766
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, each of the tiers including memory cells and a control gate for the memory cells, each of the tiers including first transistors connected in series between the control gate in a respective tier and a conductive line, and second transistors connected in series between the control gate in the respective tier and the conductive line, the second transistors connected in parallel with the first transistors between the control gate and the conductive line, conductive joints coupled to channel regions of the first and second transistors, and gates for the first transistors and second transistors, each of the gates shared by one of the first transistors and one of the second transistors.
    Type: Application
    Filed: August 29, 2024
    Publication date: December 19, 2024
    Inventors: Jun Fujiki, Yoshiaki Fukuzumi, Akira Goda
  • Patent number: 12170113
    Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: December 17, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey S. McNeil, Kishore Kumar Muchherla, Sead Zildzic, Akira Goda, Jonathan S. Parry, Violante Moschiano
  • Publication number: 20240413145
    Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. The microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.
    Type: Application
    Filed: August 19, 2024
    Publication date: December 12, 2024
    Inventors: Aaron S. Yip, Kunal R. Parekh, Akira Goda