Patents by Inventor Akira Goda

Akira Goda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11081497
    Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Surthi, Richard J. Hill, Byeung Chul Kim, Akira Goda
  • Patent number: 11074271
    Abstract: A database management system (DBMS) performs, in response to a conversion request to convert a store format of a table in a database, a process (base type change process) for changing a store format indicated by information (base type) indicating the store format of the table to a store format according to the conversion request, and performs a data conversion process asynchronously with the aforementioned process. In an import process after the base type change process, the DBMS imports, into the table, a chunk in the store format indicated by the base type after change. In the data conversion process, the DBMS converts a chunk in a store format different from the store format indicated by the base type into a chunk in the store format indicated by the base type.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: July 27, 2021
    Assignees: HITACHI, LTD., THE UNIVERSITY OF TOKYO
    Inventors: Taro Fujimoto, Takuya Isozaki, Akira Shimizu, Kazuo Goda, Yuto Hayamizu, Masaru Kitsuregawa
  • Patent number: 11075163
    Abstract: Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Peter Sean Feeley, Akira Goda
  • Publication number: 20210217730
    Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.
    Type: Application
    Filed: January 14, 2020
    Publication date: July 15, 2021
    Inventors: Kunal R. Parekh, Paolo Tessariol, Akira Goda
  • Publication number: 20210217768
    Abstract: Some embodiments include a method of forming a memory device. An assembly is formed to have channel structures extending through a stack of alternating insulative and conductive levels and into a first material under the stack. The assembly is inverted so that the first material is above the stack, and so that first regions of the channel structures are under the stack. At least some of the first regions are electrically coupled with control circuitry. At least some of the first material is removed, and second regions of the channel structures are exposed. Conductively-doped semiconductor material is formed adjacent the exposed second regions of the channel structures. Dopant is out-diffused from the conductively-doped semiconductor material into the channel structures. Some embodiments include memory devices (e.g., NAND memory assemblies).
    Type: Application
    Filed: January 15, 2020
    Publication date: July 15, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Yoshiaki Fukuzumi, Akira Goda
  • Patent number: 11056571
    Abstract: A memory cell comprises, in the following order, channel material, a charge-passage structure, programmable material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. The first and third materials comprise SiO2. The second material has a thickness of 0.4 nanometer to 5.0 nanometers and comprises SiOx, where “x” is less than 2.0 and greater than 0. Other embodiments are disclosed.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ankit Sharma, Akira Goda
  • Publication number: 20210200461
    Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.
    Type: Application
    Filed: October 23, 2020
    Publication date: July 1, 2021
    Inventors: Kishore Kumar Muchherla, Mark A. Helm, Giuseppina Puzzilli, Peter Feeley, Yifen Liu, Violante Moschiano, Akira Goda, Sampath K. Ratnam
  • Publication number: 20210202751
    Abstract: An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure coupled adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.
    Type: Application
    Filed: February 4, 2020
    Publication date: July 1, 2021
    Inventors: Akira Goda, Marc Aoulaiche
  • Publication number: 20210174874
    Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.
    Type: Application
    Filed: September 21, 2020
    Publication date: June 10, 2021
    Inventors: Akira Goda, Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat
  • Patent number: 11024643
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Guangyu Huang, Haitao Liu, Chandra Mouli, Justin B. Dorhout, Sanh D. Tang, Akira Goda
  • Patent number: 11018255
    Abstract: A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Guangyu Huang, Chandra V. Mouli, Akira Goda, Deepak Chandra Pandey, Kamal M. Karda
  • Publication number: 20210134825
    Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.
    Type: Application
    Filed: January 8, 2021
    Publication date: May 6, 2021
    Inventors: Haitao Liu, Kamal M. Karda, Gurtej S. Sandhu, Sanh D. Tang, Akira Goda, Lifang Xu
  • Publication number: 20210125669
    Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.
    Type: Application
    Filed: October 26, 2020
    Publication date: April 29, 2021
    Inventors: Akira Goda, Haitao Liu, Changhyun Lee
  • Publication number: 20210118508
    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.
    Type: Application
    Filed: November 2, 2020
    Publication date: April 22, 2021
    Inventors: Benben Li, Akira Goda, Ramey M. Abdelrahaman, Ian C. Laboriante, Krishna K. Parat
  • Patent number: 10985251
    Abstract: Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Minsoo Lee, Akira Goda
  • Patent number: 10937482
    Abstract: A memory cell comprises channel material, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen. Other embodiments are disclosed.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ankit Sharma, Haitao Liu, Albert Fayrushin, Akira Goda, Kamal M. Karda
  • Publication number: 20210057434
    Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Shyam Surthi, Richard J. Hill, Byeung Chul Kim, Akira Goda
  • Publication number: 20210057424
    Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Kamal M. Karda, Akira Goda, Sanh D. Tang, Gurtej S. Sandhu, Litao Yang, Haitao Liu
  • Publication number: 20210043259
    Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Inventor: Akira Goda
  • Publication number: 20210035630
    Abstract: One embodiment of a method for programming multiple-level memory cells includes programming lower page data to memory cells in a first pass of a multiple-pass programming operation. The method includes programming higher page data to the memory cells in a second pass of the multiple-pass programming operation such that higher page data subject to the programmed lower page data is programmed prior to higher page data subject to erase data.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Changhyun Lee, Akira Goda, William C. Filipiak