Patents by Inventor Akira Goda

Akira Goda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149511
    Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Kunal R. Parekh, Paolo Tessariol, Akira Goda
  • Publication number: 20250151281
    Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.
    Type: Application
    Filed: January 8, 2025
    Publication date: May 8, 2025
    Inventors: Haitao Liu, Kamal M. Karda, Gurtej S. Sandhu, Sanh D. Tang, Akira Goda, Lifang Xu
  • Patent number: 12293790
    Abstract: Memories might include a controller configured to cause the memory to apply a first voltage level indicative of a data state of a memory cell of an array of memory cells to a control gate of a transistor, retain the first voltage level on the control gate of the transistor, connect a first source/drain of the transistor to a data line corresponding to the memory cell while applying a second voltage level to a second source/drain of the transistor and while retaining the first voltage level on the control gate of the transistor, and apply a programming pulse to a control gate of the memory cell while the data line is connected to the first source/drain of the transistor.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: May 6, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Koichi Kawai, Yoshihiko Kamata, Akira Goda
  • Publication number: 20250140322
    Abstract: Erase operations can be performed selectively on one of erase blocks or a memory array coupled to the same string by creating a pseudo PN junction that is located adjacent to the selected erase block. The pseudo PN junction is created by including channel inversion at least on those portions of the string coupled to unselected erase blocks, which further creates a flow of electrons. As a result of the channel inversion (along with channel accumulation created adjacent to the channel inversion), the flow of gate induced drain leakage (GIDL) holes are further generated from the pseudo PN junction and GIDL holes are induced to tunnel into memory cells of the selected erase block.
    Type: Application
    Filed: July 10, 2024
    Publication date: May 1, 2025
    Inventors: Shyam Sunder Raghunathan, Yingda Dong, Akira Goda, Leo Raimondo
  • Publication number: 20250140317
    Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.
    Type: Application
    Filed: January 2, 2025
    Publication date: May 1, 2025
    Inventors: Paing Z. Htet, Akira Goda, Eric N. Lee, Jeffrey S. McNeil, Junwyn A. Lacsao, Kishore Kumar Muchherla, Sead Zildzic, Violante Moschiano
  • Publication number: 20250140323
    Abstract: An apparatus comprises a memory array comprising a plurality of physical blocks of memory cells each comprising more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block. A controller can operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block. The second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block.
    Type: Application
    Filed: July 23, 2024
    Publication date: May 1, 2025
    Inventors: Xiangang Luo, Kishore K. Muchherla, Hong Lu, Akira Goda, Shyam Sunder Raghunathan, Peter Feeley, Emilio Camerlenghi, Paolo Tessariol
  • Publication number: 20250130736
    Abstract: A processing device in a memory sub-system determines that an amount of host data in a first portion of a memory device configured as a program buffer satisfies a buffer threshold criterion and initiates an initial program pass of first host data from the program buffer to a second portion of the memory device configured as a primary memory. The processing device further determines that the first host data is to be evicted from the program buffer, and initiating a final program pass of the first host data from the program buffer to the primary memory.
    Type: Application
    Filed: September 30, 2024
    Publication date: April 24, 2025
    Inventors: Kishore Kumar Muchherla, Akira Goda, Huai-Yuan Tseng, David Scott Ebsen
  • Publication number: 20250133740
    Abstract: Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 24, 2025
    Inventors: Akira Goda, Haitao Liu, Jin Chen, Guangyu Huang, Mojtaba Asadirad
  • Patent number: 12284805
    Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: April 22, 2025
    Assignee: Lodestar Licensing Group LLC
    Inventors: Kamal M. Karda, Akira Goda, Sanh D. Tang, Gurtej S. Sandhu, Litao Yang, Haitao Liu
  • Publication number: 20250124982
    Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.
    Type: Application
    Filed: October 30, 2024
    Publication date: April 17, 2025
    Inventors: Akira Goda, Shafqat Ahmed, Khaled Hasnat, Krishna K. Parat
  • Patent number: 12266407
    Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: April 1, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee, David Scott Ebsen, Dung Viet Nguyen, Akira Goda
  • Publication number: 20250087275
    Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. A first string of the plurality of strings can comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block: apply a voltage having a first value to a sense line coupled to the plurality of strings; apply a voltage having a second value less than the first value to the first group of access lines; and apply a voltage having a third value less than the second value to the second group of access lines.
    Type: Application
    Filed: July 10, 2024
    Publication date: March 13, 2025
    Inventors: Shyam Sunder Raghunathan, Yingda Dong, Akira Goda
  • Patent number: 12249364
    Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: March 11, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Huai-Yuan Tseng, Akira Goda, Kishore Kumar Muchherla, James Fitzpatrick, Tomoharu Tanaka, Eric N. Lee, Dung V. Nguyen, David Ebsen
  • Publication number: 20250077416
    Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.
    Type: Application
    Filed: July 23, 2024
    Publication date: March 6, 2025
    Inventors: Huai-Yuan Tseng, Xiangyu Tang, Eric N. Lee, Haibo Li, Kishore Kumar Muchherla, Akira Goda
  • Publication number: 20250077415
    Abstract: An apparatus can comprise a memory array comprising a plurality of erase blocks and a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller coupled to the memory array can be configured to: receive a write command corresponding to data to be written to the memory array; determine a temperature classification for the data to which the write command corresponds; and, based on the determined temperature classification for the data, route the data to a first write cursor or to one of a number of different write cursors.
    Type: Application
    Filed: July 12, 2024
    Publication date: March 6, 2025
    Inventors: Kishore K. Muchherla, Hong Lu, Mark Ish, Akira Goda
  • Publication number: 20250078932
    Abstract: A system includes a memory device including a memory array and processing logic, operatively coupled with the memory array, to perform operations including identifying a set of cells of the memory array to be programmed with dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 6, 2025
    Inventors: Jeffrey S. McNeil, Kishore Kumar Muchherla, Sead Zildzic, Akira Goda, Jonathan S. Parry, Violante Moschiano
  • Publication number: 20250053301
    Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Jeffrey S. McNeil, Jonathan S. Parry, Ugo Russo, Akira Goda, Kishore Kumar Muchherla, Violante Moschiano, Niccolo' Righetti, Silvia Beltrami
  • Patent number: 12219772
    Abstract: Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: February 4, 2025
    Inventors: Akira Goda, Haitao Liu, Jin Chen, Guangyu Huang, Mojtaba Asadirad
  • Patent number: 12216915
    Abstract: Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Animesh R. Chowdhury, Kishore K. Muchherla, Nicola Ciocchini, Akira Goda, Jung Sheng Hoei, Niccolo′ Righetti, Jonathan S. Parry
  • Patent number: 12217799
    Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Paing Z. Htet, Akira Goda, Eric N. Lee, Jeffrey S. McNeil, Junwyn A. Lacsao, Kishore Kumar Muchherla, Sead Zildzic, Violante Moschiano