Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

Abstract: A memory device comprises an array of memory cells organized into a plurality of wordlines, and a processing device to perform processing operations that receive a program command specifying a memory unit and data comprising first received data, where the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines. The processing operations also program the specified data to the memory unit by programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, and programming the first data pattern to the first retired boundary wordline.

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.

Abstract: A memory device to use added known data as part of data written to memory cells with redundant data generated according to an error correction code (ECC). The code rate of the ECC may limit its capability to recover from excessive errors in the stored data. To reduce the errors, the added data retrieved from the memory cells can be corrected without using the ECC. Subsequently, remaining errors can be corrected via the ECC. Optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. Different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.

Abstract: A first set of host data items are programmed to first memory pages residing at a first region of a memory sub-system. A second set of host data items are programmed to second memory pages residing at the first region. A determination is made that a sequence at which the first set of host data items and the second set of host data items are programmed does not correspond to a target sequence associated with the memory sub-system. One or more of the first set of host data items are copied from one or more first memory pages to a second region of the memory sub-system that is allocated to store host data items initially programmed to first memory pages at the memory sub-system. One or more of the second set of host data items are copied from one or more second memory pages to a third region of the memory sub-system to store host data items that are programmed to second pages at the memory sub-system.

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.

Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.

Abstract: A device includes an array of memory cells with a first word line coupled to at least a subset of the array of memory cells and control logic coupled to the first word line. The control logic to detect, within a queue, a first read command to read first data from a first page of the subset and a second read command to read second data from a second page of the subset. The control logic is further to cause a voltage applied to the first word line to move to a target value. The control logic is further to cause a page buffer to sense the first data from a first bit line coupled to the first page and to sense the second data from a second bit line coupled to the second page. The control logic is further to cause the first word line to be discharged.

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.

Abstract: One embodiment of a memory device includes an array of multiple-level memory cells and a controller. The controller is configured to program the multiple-level memory cells via a multiple-pass programming operation, the multiple-pass programming operation to program lower page data in a first pass and program higher page data in a second pass such that memory cells to be programmed to a higher level are programmed in parallel with memory cells to be programmed to a lower level.

Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: Control logic in a memory device determines to initiate a string read operation on a first memory string of a plurality of memory strings in a block of a memory array of the memory device, the block comprising a plurality of wordlines, wherein each of the plurality of memory strings comprises a plurality of memory cells associated with the plurality of wordlines, and wherein the first memory string is designated as a sacrificial string. The control logic further causes a read voltage to be applied to each of the plurality of wordlines of the memory array concurrently and senses a level of current flowing through the first memory string designated as the sacrificial string while the read voltage is applied to each of the plurality of wordline. In addition, the control logic identifies, based on the level of current flowing through the first memory string designated as the sacrificial string, whether a threshold level of read disturb has occurred on the block.

Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.