Patents by Inventor Akira Kotabe
Akira Kotabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8605476Abstract: A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.Type: GrantFiled: December 3, 2010Date of Patent: December 10, 2013Assignee: Elpida Memory, Inc.Inventors: Takenori Sato, Kazuhiko Kajigaya, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Satoru Akiyama
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Publication number: 20130322188Abstract: A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation.Type: ApplicationFiled: June 5, 2013Publication date: December 5, 2013Applicant: Hitachi, Ltd.Inventors: Goichi Ono, Yusuke Kanno, Akira Kotabe
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Patent number: 8587117Abstract: A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal.Type: GrantFiled: April 25, 2012Date of Patent: November 19, 2013Assignee: Elpida Memory, Inc.Inventors: Shinichi Takayama, Kazuo Ono, Tomonori Sekiguchi, Akira Kotabe, Yoshimitsu Yanagawa
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Publication number: 20130292630Abstract: The technical problem to be solved is to achieve high density with simple manufacturing process to decrease bit costs of memory. A semiconductor memory device according to a first aspect of the present invention includes a variable resistance material layer and a channel layer that are connected in series between a first diffusion layer and a metal wire, thereby separating the metal wire and a channel semiconductor layer. A semiconductor memory device according to a second aspect of the present invention includes a variable resistance material layer electrically connecting channel semiconductor layers opposed to each other in a first direction and electrically connecting channel semiconductor layers adjacent to each other in a second direction, wherein a plurality of the channel semiconductor layers is disposed in the second direction.Type: ApplicationFiled: March 13, 2013Publication date: November 7, 2013Applicant: HITACHI, LTD.Inventors: Yoshitaka Sasago, Akira Kotabe
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Publication number: 20130258793Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.Type: ApplicationFiled: May 23, 2013Publication date: October 3, 2013Applicant: ELPIDA MEMORY, INC.Inventors: Shinichi TAKAYAMA, Akira KOTABE, Kiyoo ITOH, Tomonori SEKIGUCHI
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Publication number: 20130193507Abstract: A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.Type: ApplicationFiled: January 26, 2012Publication date: August 1, 2013Applicant: Elpida Memory, Inc.Inventors: Soichiro YOSHIDA, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe
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Patent number: 8472273Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.Type: GrantFiled: May 27, 2011Date of Patent: June 25, 2013Assignee: Elpida Memory, Inc.Inventors: Shinichi Takayama, Akira Kotabe, Kiyoo Itoh, Tomonori Sekiguchi
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Patent number: 8467217Abstract: The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal.Type: GrantFiled: February 23, 2011Date of Patent: June 18, 2013Assignee: Elpida Memory, Inc.Inventors: Shinichi Takayama, Kazuhiko Kajigaya, Akira Kotabe, Satoru Akiyama, Tomonori Sekiguchi
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Publication number: 20130057326Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.Type: ApplicationFiled: August 29, 2012Publication date: March 7, 2013Inventors: Yoshimitsu YANAGAWA, Tomonori Sekiguchi, Akira Kotabe, Takamasa Suzuki
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Publication number: 20120267792Abstract: A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal.Type: ApplicationFiled: April 25, 2012Publication date: October 25, 2012Applicant: Elpida Memory, Inc.Inventors: Shinichi TAKAYAMA, Kazuo ONO, Tomonori SEKIGUCHI, Akira KOTABE, Yoshimitsu YANAGAWA
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Publication number: 20120249180Abstract: A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the fifth transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.Type: ApplicationFiled: March 23, 2012Publication date: October 4, 2012Inventors: Takamasa SUZUKI, Akira Kotabe, Tomonori Sekiguchi, Riichiro Takemura
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Publication number: 20110292709Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.Type: ApplicationFiled: May 27, 2011Publication date: December 1, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Shinichi TAKAYAMA, Akira KOTABE, Kiyoo ITOH, Tomonori SEKIGUCHI
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Publication number: 20110205820Abstract: The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal.Type: ApplicationFiled: February 23, 2011Publication date: August 25, 2011Inventors: Shinichi Takayama, Kazuhiko Kajigaya, Akira Kotabe, Satoru Akiyama, Tomonori Sekiguchi
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Publication number: 20110176379Abstract: A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.Type: ApplicationFiled: January 18, 2011Publication date: July 21, 2011Inventors: Shinichi TAKAYAMA, Akira Kotabe, Kazuo Ono, Tomonori Sekiguchi, Yoshimitsu Yanagawa, Riichiro Takemura
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Publication number: 20110134678Abstract: A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.Type: ApplicationFiled: December 3, 2010Publication date: June 9, 2011Applicant: Elpida Memory, Inc.Inventors: Takenori Sato, Kazuhiko Kajigaya, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Satoru Akiyama
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Patent number: 7907442Abstract: In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN3 and MN4) and capacitively coupled to the input nodes of the data latch circuit via gates of first MOS transistors (MP1 and MP2) respectively. In this separated state, the first and second signal lines and the input nodes of the data latch circuit are precharged to different voltages, so that the gate-to-source and drain-to-source voltages of the first MOS transistors are controlled by the voltages of the first and second signal lines respectively.Type: GrantFiled: October 12, 2006Date of Patent: March 15, 2011Assignee: Renesas Electronics CorporationInventors: Naoki Kitai, Satoru Hanzawa, Akira Kotabe
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Patent number: 7750712Abstract: A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.Type: GrantFiled: December 5, 2008Date of Patent: July 6, 2010Assignee: Elpida Memory, Inc.Inventors: Akira Ide, Yasuhiro Takai, Akira Kotabe, Tomonori Sekiguchi, Riichiro Takemura, Satoru Akiyama
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Publication number: 20100073999Abstract: In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN3 and MN4) and capacitively coupled to the input nodes of the data latch circuit via gates of first MOS transistors (MP1 and MP2) respectively. In this separated state, the first and second signal lines and the input nodes of the data latch circuit are precharged to different voltages, so that the gate-to-source and drain-to-source voltages of the first MOS transistors are controlled by the voltages of the first and second signal lines respectively.Type: ApplicationFiled: October 12, 2006Publication date: March 25, 2010Inventors: Naoki Kitai, Satoru Hanzawa, Akira Kotabe
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Publication number: 20090146716Abstract: A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.Type: ApplicationFiled: December 5, 2008Publication date: June 11, 2009Inventors: Akira Ide, Yasuhiro Takai, Akira Kotabe, Tomonori Sekiguchi, Riichiro Takemura, Satoru Akiyama
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Patent number: 7180768Abstract: Disclosed is a method of improving stability of a memory cell in read mode in an SRAM including a memory cell comprising two access MOS transistors and two drive MOS transistors. The magnitude of voltage between gate and source of an access transistor of a memory cell connected to a selected word line is controlled to be smaller than a power-supply voltage by controlling the voltage of selected word line WL in read mode.Type: GrantFiled: June 29, 2004Date of Patent: February 20, 2007Assignee: Renesas Technology Corp.Inventors: Akira Kotabe, Kenichi Osada, Masahiro Moniwa, Shiro Kamohara