Abstract: A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

Abstract: A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film is composed of a first portion disposed on a side wall portion of the trench and a second portion disposed on upper and bottom portions of the trench. The first portion is composed of a first oxide film, a nitride film, and a second oxide film. The second portion is composed of only an oxide film and has a thickness thicker than that of the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be mitigated, and a decrease in withstand voltage at that portions can be prevented.

Abstract: On a TEOS (tetraethyl ortho silicate) film and a surface of an aluminum wiring formed on a P-type silicon substrate, there is formed a low hydrogen content plasma SiN film on which a high hydrogen content plasma SiN film is laminated. The low hydrogen content plasma SiN film is lower in content of hydrogen than the high hydrogen content plasma SiN film. Accordingly, even when hydrogen is about to go toward and into the P-type silicon substrate side from the high hydrogen content plasma SiN film, the entry of hydrogen is blocked by the low hydrogen content plasma SiN film in which amount of Si--H bonds is reduced.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device includes a semiconductor element. A silicon nitride film covers the semiconductor element. The silicon nitride film is made of Si.sub.X N.sub.Y H.sub.Z, where X, Y, and Z denote atomic fractions of Si, N, and H resptively. The silicon nitride film relates to an optical absorption edge wavelength shorter than 254 nm. A mean area of regions surrounded by crystal-like grain boundaries at a surface of the silicon nitride film is equal to 4.5.times.10.sup.4 nm.sup.2 or more. The semiconductor element may include a memory element from which information can be erased by exposure to ultraviolet rays.

Abstract: The insulating ability of a semiconductor device of two-layer gate electrode structure, such as EPROM, is improved at the upper surface of the first gate electrode as well as at the upper and lower edge parts of the first gate electrode. A LOCOS film is formed on a semiconductor substrate, and a floating gate is formed by patterning. Next, the first oxide film is formed on the floating gate, and then the first oxide film is etched out. Subsequently, the second oxide film is formed on the floating gate, and a control gate is formed on the floating gate using the second oxide film as an inter-layer insulating film. As a result of these two oxidations of the first and second oxide films and the removal of the first oxide film, the asperity of the upper surface of the floating gate is removed, and the upper and lower edge parts thereof are shaped into a round form.

Abstract: The present invention involves a vertical type semiconductor device whereby miniaturization and lowered ON resistance of a cell within the device can be achieved without impairing the functioning of the device. The line width of the gate electrode is made smaller to meeting the demand for miniaturization of the cell while the distance between the channel regions which are diffused into the portions below the gate during double diffusion remains virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. While the width of the gate electrode is set to be smaller, the mask members used during double diffusion are attached to the side walls of the gate electrode, where their width allows the source region to diffuse to the portion under the gate. Accordingly, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.

Abstract: On TEOS (tetraethyl ortho silicate) film and a surface of an aluminum wiring formed on a P-type silicon substrate, there is formed a low hydrogen content plasma SiN film on which a high hydrogen content plasma SiN film is laminated. The low hydrogen content plasma SiN film is lower in content of hydrogen than the high hydrogen content plasma SiN film. Accordingly, even when hydrogen is about to go toward and into the P-type silicon substrate side from the high hydrogen content plasma SiN film, the entry of hydrogen is blocked by the low hydrogen content plasma SiN film in which amount of Si-H bonds is reduced.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: A power semiconductor device having a current detecting function comprising a detection part that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part.

Abstract: A semiconductor device includes a semiconductor element. A silicon nitride film covers the semiconductor element. The silicon nitride film is made of Si.sub.X N.sub.Y H.sub.Z, where X, Y, and Z denote atomic fractions of Si, N, and H respectively. The silicon nitride film relates to an optical absorption edge wavelength shorter than 254 nm. A mean area of regions surrounded by crystal-like grain boundaries at a surface of the silicon nitride film is equal to 4.5.times.10.sup.4 nm.sup.2 or more. The semiconductor element may include a memory element from which information can be erased by exposure to ultraviolet rays.

Abstract: An intelligent power element has integrated DMOS transistors and control elements such as NMOS transistors. Impurity concentration inside a channel well (4) of each DMOS transistor is denser than that at the surface thereof. This results in reducing the reach-through withstand voltage of the DMOS transistor to less than that of the NMOS transistor. As a result, a reach-through phenomenon occurs on the DMOS transistor having a higher allowable (withstand) current before it occurs on the NMOS transistor having a lower allowable current. To provide the same effect, the reach-through withstand voltage of the DMOS transistor may be decreased by forming an internal high concentration well (201) at an upper part of a deep main well (31) of the DMOS transistor. The well (201) is shallower than the main well (31) and does not extend under a gate electrode (71).

Abstract: A power DMOS semiconductor device is producible with standard processes and provides improved current detecting accuracy. The device involves main wells (41), subwells (42), and a line well (43), which is independent of the main wells and subwells. These wells are formed by doping the surface of a semiconductor substrate (1) with well forming impurities. The line well surrounds the subwells with a predetermined distance away from the subwells, to relax an electric field on the surface of the substrate. Gate electrodes (71, 72) are patterned to form a line opening (10), which surrounds the subwells. The line opening serves as a mask when forming the line well by doping the surface of the substrate with the well forming impurities. Accordingly, the width of a region between the line well and an adjacent subwell will not fluctuate.

Abstract: A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

Abstract: A method fabricates a semiconductor device having a sidewall made from an insulation film at each side of a gate electrode portion. The method forms a polysilicon gate electrode (11a) on a gate oxide film (10) in a predetermined region on an n.sup.- epitaxial layer (2). A CVD silicon oxide film (15) having a predetermined thickness is formed over the polysilicon gate electrode material (11a) on the n.sup.- epitaxial layer (2). A magnetron enhanced reactive ion etching apparatus is used to etch the CVD silicon oxide film (15) while pouring a CHF.sub.3 gas made by coupling carbon, hydrogen, and fluorine and an N.sub.2 gas onto the etched material, such that the CVD silicon oxide film (15) is left only at each side of the polysilicon gate electrode material (11a), to form a sidewall (16). To avoid electrodes of the magnetron enhanced reactive ion etching apparatus from staining, CHF.sub.3 /He/N.sub.2 /O.sub.2 may be used for etching.

Abstract: A power semiconductor device having current detecting function comprising a detection pert that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part.

Abstract: A power DMOS semiconductor device providing improved current detection accuracy can be produced using standard pocessess. The device includes main wells, subwells and a line well which is independent of the main wells and subwells. These wells are formed by doping the surface of a semiconductor substrate with well-forming impurities. The line well surrounds the subwells at a predetermined distance away from the subwells to relax an electric field on the surface of the substrate. Gate electrodes are patterned to form a line opening which surrounds the subwells. The line opening serves as a mask when forming the line well by doping the surface of the substrate with the well-forming impurities. Accordingly, the width of a region between the line well and an adjacent subwell will not fluctuate.

Abstract: The present invention has as an object the provision of a vertical type semiconductor device whereby miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.The line width of the gate electrode is made smaller to meet the demand for miniaturization of the cell, but the distance between the channel regions diffused into the portions below the gate at the time of double diffusion is kept to be virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. Here, the reason for making the line width of the gate electrode smaller is for securing an area for the source contact.The point is that, while the width of the gate electrode is set to be smaller, the mask members as the mask for double diffusion, having the width allowing the source region to diffuse to the portion under the gate, are attached to the side walls of the gate electrode.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.