Abstract: Link capacitors are used to establish connection between joining-points of coupling capacitors and inverters in an inverter chopper comparator array, in order to reduce injected electric charge variation due to feedthrough. Some of the comparators in the comparator array, arranged at each end thereof, constitute a redundant comparator array without connection to a logic circuit that is used to obtain an A/D conversion output. This reduces the effects of the device parameter variations in the comparator array whereby a high accuracy voltage comparison is achieved, and noise-resistant strength is improved.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition.

Abstract: There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption.An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: According to the present invention, an A/D converter for receiving an input voltage and outputting a digital signal representing a level of the input voltage by a number n (where n is a natural number equal to or larger than 2) of upper bits and a number m (where m is a natural number equal to or larger than 2) of lower bits is provided.

Abstract: The present invention discloses an improved latch circuit. In the latch circuit, a composite gate takes in a basic clock signal and a delayed clock signal which is delayed by a delay circuit for a specific amount with respect to the basic clock signal, and puts out to a second drive circuit a first signal identical in waveform with the basic block signal, and further puts out to a first drive circuit a second signal that is delayed in the rising timing with respect to the first signal. As a result of such arrangement, when a transition is made from a feedback period during which an input switch has an off state while a feedback switch has an on state to a sampling period during which the input switch has an on state while the feedback switch has an off state, neither the input switch nor the feedback switch has an on state.

Abstract: An analog memory circuit of the present invention includes: a recording circuit for recording and holding an input analog signal as a charge and for reading out the analog signal after deterioration of the analog signal caused by leakage of the charge in a holding operation is eliminated; a selecting circuit for controlling an operation of the recording circuit; and a driving circuit for supplying a predetermined constant voltage to the recording circuit, wherein the recording circuit includes: an input/output terminal for inputting and outputting the analog signal; a first capacitor having a first electrode and a second electrode, for recording and holding the analog signal as the charge; and a second capacitor connected between the second electrode of the first capacitor and a reference potential, for holding a charge leaked from the first capacitor, and wherein an amount of charge corresponding to an amount of leaked charge held in the second capacitor is restored to the first capacitor with predetermined

Abstract: In an interpolative modulator, a signal which varies by only .+-.1 with one clock from a 1-bit quantizer is used as a shift-direction control signal. The shift-direction control signal is given to a bidirectional shift register. The bidirectional shift register shifts data based on the value of the shift-direction control signal that has been received. The output from the bidirectional shift register is given as a control signal to a resistive-ladder-type D/A converter. The resistive-ladder-type D/A converter outputs an analog potential corresponding to a switch selected by the above control signal. Therefore, if a delay difference occurs between any two bits, two adjacent switches are simply selected simultaneously, so that the output from the resistive-ladder-type D/A converter varies continuously. Consequently, there can be provided an oversampling D/A converter of resistive-ladder type with high accuracy and an increased yield, which is free from glitch (transiently generated noise).

Abstract: The present invention provides a first-order delta-sigma AD converter adapted to conduct noise shaping and having a quantizer arranged such that, when the amplitude of an input signal entered into the quantizer is small, the amplitude of a difference signal between the input signal entered into the quantizer and an output signal therefrom, is small. It is therefore possible to achieve an efficient AD- or DA-converter reduced in power consumption, which satisfies the transmission characteristics of the specifications of CCITT G.714 based on a method of PCM-encoding an audio frequency band signal stipulated in the specifications of CCITT G.711.

Abstract: The present invention discloses an improved analog-to-digital converter. A second sampling circuit samples the voltage difference between an analog signal and a reference voltage, before a first sampling circuit moves to a follow operation from a sample operation. Owing to pipelining by the first and second sampling circuits, even after the first sampling circuit moves to a follow operation, the difference between an analog signal and a reference voltage is still applied to a logical-level amplifier. The output of the logical-level amplifier, amplified to a logical voltage, is converted by a logic device into an A/D conversion output. Therefore, ADC differential non linearity error can be reduced.

Abstract: Link capacitors are used to establish connection between joining-points of coupling capacitors and inverters in an inverter chopper comparator array, in order to reduce injected electric charge variation due to feedthrough. Some of the comparators in the comparator array, arranged at each end thereof, constitute a redundant comparator array without connection to a logic circuit that is used to obtain an A/D conversion output. This reduces the effects of the device parameter variations in the comparator array, whereby a high accuracy voltage comparison is achieved, and noise-resistant strength is improved.

Abstract: Analog-to-digital conversion method and device using triangular vertex solution are disclosed. The method includes the steps of defining a first and a second boundary value between which a quantity to be analog-to-digital converted resides, multiplying a difference between the first boundary value and the quantity to be converted by a first coefficient to produce a first physical quantity, multiplying a difference between the second boundary value and the quantity to be converted by a second coefficient to produce a second physical quantity, comparing the first and second physical quantities to obtain a comparison result, and logically converting the comparison result into a digital value.

Abstract: By making a folded waveform of a folding circuit sharp, the number of elements used in an ADC is reduced and less power consumption is achieved. A folding circuit is composed of a plurality of master-comparator latches, a pair of wiring means for master-to-slave connection, and a slave latch. By means of the wiring means, the non-inverted outputs and the inverted outputs of the master-comparators latches are alternately drawn in the order of magnitude of reference voltages, superimposed, and fed into a pair of inputs of the slave latch. A Gray code signal is directly encoded by an encoder according to the output of the slave latch. A folded signal, which is the output of the folding circuit, takes a sharp waveform. The number of slave latches can be reduced. No XOR gates are required.

Abstract: A parallel type analog to digital (A/D) converter in which an input signal and reference voltages are differentially amplified by differential converting circuits, interpolation resistors are inserted between the outputs and between the complementary outputs of the differential converting circuits, and a tap voltage between the interpolation resistors is A/D converted, so that the A/D converter can operate at a high accuracy and at a high speed.

Abstract: A plurality of different reference voltages are generated. A set of differential conversion circuits has first input terminals subjected in common to an analog input signal and second input terminals subjected to the respective reference voltages, and converts differences between voltages at the first and second input terminals into differential output voltages. A first A/D conversion circuit compares the analog input signal with the reference voltages to perform a higher-order A/D conversion of the input analog signal. At least two of the differential output voltages are selected. An interval between the selected differential output voltages is divided, and divided voltages are generated in accordance with the division. A second A/D conversion circuit compares the divided voltages to perform a lower-order A/D conversion of the analog input signal.

Abstract: A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current is allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.

Abstract: An improved differential voltage buffer amplifier circuit of the type having a pair of transistors connected in emitter-follower configuration with an input differential voltage signal applied between the bases thereof and a load resistor connected between the emitters thereof, which further includes a compensation circuit for eliminating a voltage transfer error resulting from current flow through the load, for thereby achieving a voltage gain value that is very close to one. The buffer circuit is particularly advantageous for use in a new high-accuracy A-D converter which is suitable for integrated circuit implementation.

Abstract: A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current in allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.

Abstract: A buffer circuit includes an operational amplifier circuit, a first emitter follower circuit whose base is driven by an output of the operational amplifier circuit and whose output is fed back to an inverting input terminal of the operational amplifier circuit, and a second emitter follower circuit whose base is also driven by the output of the operational amplifier circuit and whose output drives a load circuit. In another form, the buffer circuit also includes a current control circuit that detects operation current flowing through the second emitter follower circuit, thereby controlling the operation current flowing through the first emitter follower circuit.