Abstract: The manufacturing stability can be improved while effectively inhibiting the short-channel effect in the transistor according to the present invention. A halo impurity having a conductivity type opposite to a first conductivity type of a first impurity is ion-implanted into the silicon substrate 101, and thereafter, the first impurity having the first conductivity type is ion-implanted, and then a laser beam is irradiated on a region where the first impurity is doped under a condition so that the silicon substrate 101 is not melted to form a p-type halo region 113 and a n-type extension region 111. Then, the second impurity having the first conductivity type is ion-implanted into the silicon substrate 101, and a laser beam is irradiated on a region where the second impurity is doped under a condition so that the silicon substrate 101 is not melted to form a n-type source/drain region 109.

Abstract: In a method for manufacturing a semiconductor device, gate insulation films and gate electrodes are first formed on a substrate. An impurity is implanted into each gate electrode. Next, a first heat treatment is performed to the substrate for diffusing the impurity in the gate electrodes. After the heat treatment, a second heat treatment is performed for releasing stress generated in the substrate in the first heat-treatment. Thereafter, an impurity is implanted into an area to become an implanted region of the substrates using the gate electrodes as masks, and a third heat treatment is performed for activating the impurity implanted.

Abstract: A manufacturing method of a semiconductor device, in which a native oxide film on a silicon substrate is removed before ion implantation is performed, and a process that the surface of the silicon substrate is liable to be oxidized, such as a resist removing process, is not to be performed after the ion implantation, is provided. At a source/drain extension region forming process after a gate electrode is formed, a pMOS region is covered with a resist, and As or P is implanted to an nMOS region by low energy implantation. After removing the resist from the pMOS region, a cover insulation film with about 20 nm thickness is disposed on the whole surface of a silicon substrate. The cover insulation film only at the pMOS region is removed by etching back, and a thin film side wall is formed on the gate electrode of the pMOS region. By removing the resist at the nMOS region, a hard mask is formed at the nMOS region, this hard mask works as a mask at the nMOS region when pMOS extension is performed.

Abstract: A fabrication method of a semiconductor device is provided, which makes it possible to form shallow extensions (e.g., 0.1 &mgr;m or less in depth) of source/drain regions of a MOSFET with a double drain structure. In the step (a), a gate electrode is formed over a main surface of a single-crystal Si substrate of a first conductivity type through a gate insulating film. In the step (b), a dopant of a second conductivity type is ion-implanted into the substrate at an acceleration energy of 1 keV or lower under a condition that the amount of point defects induced in this step (b) is minimized or decreased, thereby forming first and second doped regions of the second conductivity type. In the step (c), a pair of sidewalls spacers are formed.

Abstract: A semiconductor device is manufactured by a step of forming a gate electrode on a semiconductor substrate with a gate insulation film therebetween, and using this gate electrode as a mask to implant ions to achieve a high-dose doping of impurities, thereby forming a source/drain region, using an accelerating potential for ion implantation that is lower to a value at which implantation damage is not done to the gate insulation film.

Abstract: The present invention provides a method of forming gate side wall insulation films on side walls of a gate electrode on a gate insulation film over a silicon substrate surface. The method comprises The following steps. Gate side wall insulation films are selectively formed on side walls of a gate electrode. A silicon film is selectively grown on at least any one of a top of the gate electrode and on the silicon substrate surface. Surface regions of the gate side wall insulation films are etched.

Abstract: A method of forming shallow diffusion layers in a semiconductor substrate is provided wherein the shallow diffusion layers are positioned in the vicinity of edge portions of a gate electrode and laterally extend from source/drain diffusion layers having a bottom level deeper than the shallow diffusion layers. The above method comprises the following steps. Crystal defects are selectively formed at least in predetermined shallow regions positioned in a surface region of the semiconductor substrate and in the vicinity of the edge portions of the gate electrode. The predetermined shallow regions are laterally in contact with impurity-introduced deep regions having been formed. The predetermined shallow regions have a bottom level shallower than the impurity-introduced deep regions.

Abstract: A fabrication method of a semiconductor device that enables to produce a thin film of a refractory-metal silicide at a semiconductor active film without raising any defects such as agglomeration, cracks and voids. A semiconductor active film with a thickness of at most 500 .ANG. is formed on an insulating substructure. A gate insulator film and a gate electrode are formed on the active film. An impurity is selectively doped into the active film to form source and drain regions. The remaining semiconductor active film between the source and drain regions constitutes a channel region. A refractory-metal film is formed to cover the gate electrode and the source and drain regions and is heat-treated, producing first and second silicide films through silicidation reaction of the semiconductor active film with the refractory-metal film as parts of the source and drain regions. Preferably, the refractory-metal film has a thickness of (1/2) to (1/5) times as much as that of the semiconductor active film.

Abstract: A combination of a lower thin film transistor formed on an insulating substrate and an upper thin film transistor laminated over the lower transistor has a lower channel formed in the lower transistor, an upper channel formed in the upper transistor, a lower gate electrode disposed under the lower channel, an intermediate gate electrode disposed between the lower channel and the upper channel, and an upper gate electrode disposed over the upper channel.