Abstract: A wire processing apparatus includes an applicator (60) for crimping a crimp contact onto an end of a wire (2) and solder depositing units (7, 8) for depositing solder onto an exposed core on the wire end, all of which serve as wire processing units. The applicator (60) and the solder depositing units (7, 8) are attachable to and removable from a placement section (13a) and are interchangeable with each other. Each of the solder depositing units (7, 8) includes a flux bath (15) for storing a flux liquid therein, a solder bath (16) for storing solder in a molten state therein, and a flux liquid holding tube having a holding hole for holding the flux liquid therein and capable of releasably receiving the core. The core is moved downwardly into a solder portion raised by the surface tension of the solder stored in the solder bath 16, whereby the solder is deposited on the core.

Abstract: In an electromagnetic coupling type four-point feeding loop antenna (10) comprising a tubular body (11), a loop portion (12) having a loop width (W1), four feeders (13) each having a feeder width (W2), and four electromagnetic coupling wires (17) each having a coupling wire width (W3), the loop width, the feeder width, and the coupling wire width are substantially equal to one another. A gap (&dgr;) between the feeder and the electromagnetic coupling wire is laid in a range between 0.2 mm and 0.8 mm, both inclusive, when the electromagnetic coupling type four-point feeding loop antenna has a feeding impedance of a range between 25 &OHgr; and 100 &OHgr;, both inclusive.

Abstract: In order to feed at four points to a loop portion (12) made of conductor formed around a central axis (O) in a loop fashion along a peripheral surface of a cylindrical body (11) formed by rounding a flexible insulator film member (20) around the central axis in a cylindrical fashion, each of four feeders (13) formed on the peripheral surface of the cylindrical body comprises a vertical feeding portion (131) having one end (131a) grounded and another end (131b) extending toward the loop portion, a zigzag line (132) disposed between the other end of the vertical feeding portion and the loop portion, a tap (133) for feeding from a feeding terminal (13a) to the vertical feeding portion.

Abstract: An electromagnetic coupling type four-point feeding loop antenna (10) comprises a cylindrical body (11) formed by rounding a flexible insulator film member (20) around a central axis (O) in a cylindrical fashion and a loop portion (12) made of conductor that is formed on the cylindrical body along a peripheral surface thereof around the central axis in a loop fashion. In order to feed to the loop portion at four points, four feeders (13) are formed on the peripheral surface of the cylindrical body. Between the loop portion and each of the four feeders, a gap (&dgr;1) is provided, whereby carrying out feed to the loop portion by electromagnetic coupling.

Abstract: In order to feed at four points to a loop portion (12) made of conductor formed around a central axis (O) in a loop fashion along a peripheral surface of a cylindrical body (11) formed by rounding a flexible insulator film member (20) around the central axis in a cylindrical fashion, each of four feeders (13) formed on the peripheral surface of the cylindrical body comprises a vertical feeding portion (131) having one end (131a) grounded and another end (131b) extending toward the loop portion, a zigzag line (132) disposed between the other end of the vertical feeding portion and the loop portion, a tap (133) for feeding from a feeding terminal (13a) to the vertical feeding portion.

Abstract: An electromagnetic coupling type four-point feeding loop antenna (10) comprises a cylindrical body (11) formed by rounding a flexible insulator film member (20) around a central axis (O) in a cylindrical fashion and a loop portion (12) made of conductor that is formed on the cylindrical body along a peripheral surface thereof around the central axis in a loop fashion. In order to feed to the loop portion at four points, four feeders (13) are formed on the peripheral surface of the cylindrical body. Between the loop portion and each of the four feeders, a gap (&dgr;1) is provided, whereby carrying out feed to the loop portion by electromagnetic coupling.

Abstract: In a monopole antenna having a monopole standing up on one surface of a circuit board, a metal case is provided on the other surface of the circuit board. The monopole and the metal case are covered with an exterior case. The metal case includes a base plate portion faced to the circuit board with a space kept therefrom, a side surface portion extending from a circumferential or peripheral edge of the base plate portion toward the circuit board and fixed to the circuit board, and a belt-like metal plate disposed outside the side surface portion and extending in the circumferential direction. The belt-like metal plate has a part which forms a wave-like shape of a wave traveling in the circumferential direction and is press-fitted between the side surface portion and the exterior case.

Abstract: In an adder circuit, a block carry generation logic over three consecutive digits is produced from the following equations. G0=g2+p2·g1+p2·p1·g0 /g0=/p2+/g2·/p1+/g2·/g1·/g0 In other words, the block carry generation logic /G0 is produced by a single PMOS transistor, a series circuit formed of two PMOS transistors connected in series, and a series circuit formed of three PMOS transistors connected in series. The block carry generation logic G0 is produced by a single NMOS transistor, a series circuit formed of two NMOS transistors connected in series, and a series circuit formed of three NMOS transistors connected in series. Block carry generation logics can be formed in such a way as to achieve not only a reduction of the layout area but also a higher operation rate.

Abstract: A wire processing apparatus includes an applicator (60) for crimping a crimp contact onto an end of a wire (2) and solder depositing units (7, 8) for depositing solder onto an exposed core on the wire end, all of which serve as wire processing units. The applicator (60) and the solder depositing units (7, 8) are attachable to and removable from a placement section (13a) and are interchangeable with each other. Each of the solder depositing units (7, 8) includes a flux bath (15) for storing a flux liquid therein, a solder bath (16) for storing solder in a molten state therein, and a flux liquid holding tube having a holding hole for holding the flux liquid therein and capable of releasably receiving the core. The core is moved downwardly into a solder portion raised by the surface tension of the solder stored in the solder bath 16, whereby the solder is deposited on the core.

Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction "MCSST D1" is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer "0x0000.sub.-- 00FF". The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is "ON". The multiplexer 24 outputs one of the maximum value "0x0000.sub.-- 00FF" generated by the constant generator 21, the zero value "0x0000.sub.-- 0000" generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

Abstract: In the case where a multiplier factor is a constant, if the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is larger than the number of the bits having the value of 0, a circuit for performing multiplication by using the logic NOT number of the multiplier factor, which is obtained by inverting all the bits in the multiplier factor by the logic NOT operation is generated. If the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is smaller than the number of the bits having the value of 0, the multiplier factor is divided so that an adder for adding partial products forms a well-balanced binary tree. Conversely, if the number of the bits having the value of 1 in the multiplier factor is 2 or less, an add shift multiplier for calculating partial products only with respect to the bits having the value of 1 is generated.

Abstract: A semiconductor integrated circuit includes a functional block realizing at least part of a function of the semiconductor integrated circuit. The functional block includes a plurality of basic cells and a plurality of terminal cells. Each of the plurality of terminal cells has a connector for mediating a communication between another semiconductor integrated circuit and one of the plurality of basic cells.

Abstract: A partial product adder for summing up four partial products P0, P1, P2, and P3 which are binary numbers in twos-complement representation having different weights is composed of a carry save adder consisting of an array of 4:2 compressors each having four inputs. Of the four inputs of each 4:2 compressor, the input W presents the shortest propagation delay, while the inputs Y and Z compose critical paths. To implement sign extension of the first partial product P0 having the smallest weight, a logic circuit provides, in a plurality of digit positions higher than the sign digit P0s of the first partial product, values resulting from a logic operation between the value of the sign digit P0s of the first partial product and the value of the sign digit P1s of the second partial product having the second smallest weight.

Abstract: A mantissa X.sub.Mk, which satisfies 1.ltoreq.X.sub.Mk <2, is fed to a mantissa process section in order that the iterative multiplication operation of normalized floating-point numbers X.sub.k (k=0, . . . , m), written P=X.sub.0 .times.X.sub.1 .times.X.sub.2 .times.0 . . . .times.X.sub.m, is performed. In the mantissa process section, a product represented in RB (redundant binary) number representation is stored in a register, and such a product is fed back to a multiplier without being converted into a binary number. A shifter for one-place right-shift is provided between the multiplier and the register. A converter sequentially converts each RB number stored in the register into a binary number and provides to the shifter a shift-amount signal S.sub.1 whose value varies with the result of such RB-to-binary number conversion. If a digit that is positioned upward two places from the binary point of a binary number obtained by the conversion is 0, then the value of S.sub.1 is set to 0.

Abstract: A signal cache memory controller which includes line for inputting an index section of an address is formed with a branch line which is intervened by an address delay circuit. In each of banks X and Y, a switching circuit selects the data which has been delayed in response to a select signal Sse being outputted as a cache-access address to be outputted to a tag memory. An address comparator compares a tag section of the address input through a signal line for inputting the tag section with a reference address output from the tag memory and outputs an coincidence signal if there is a coincidence therebetween. When the coincidence signal is generated and the select signal Sse is not generated, a bank-hit signal generating circuit generated a bank-hit signal Sbh, in response to which a select-signal generating circuit generates the select signal Sse. The circuit for controlling a cache memory which is divided into a plurality of banks enables the writing of data in the cache in every cycle.

Abstract: A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is .UPSILON., into consecutive N-digit sets (N is a natural number equal to or less than M) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.1 according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i (Z.sub.gi is the value of an ith set (i represents natural numbers equal to or greater than a predetermined number)) and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i and a selection circuit for selecting one of one or more numbers having the same format as that of the intermediate carry C.sub.i corresponding to the ith set and for outputting the selected number to the recoding circuit as the intermediate carry C.sub.i-1 corresponding to the (i-1)th set.

Abstract: A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is .UPSILON., into consecutive N-digit sets (N is a natural number equal to or less than M) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.i according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i (Z.sub.gi is the value of an ith set (i represents natural numbers equal to or greater than a predetermined number)) and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i and a selection circuit for selecting one of one or more numbers having the same format as that of the intermediate carry C.sub.i corresponding to the ith set and for outputting the selected number to the recoding circuit as the intermediate carry C.sub.i-1 corresponding to the (i-1)th set.