Abstract: A signal cache memory controller which includes line for inputting an index section of an address is formed with a branch line which is intervened by an address delay circuit. In each of banks X and Y, a switching circuit selects the data which has been delayed in response to a select signal Sse being outputted as a cache-access address to be outputted to a tag memory. An address comparator compares a tag section of the address input through a signal line for inputting the tag section with a reference address output from the tag memory and outputs an coincidence signal if there is a coincidence therebetween. When the coincidence signal is generated and the select signal Sse is not generated, a bank-hit signal generating circuit generated a bank-hit signal Sbh, in response to which a select-signal generating circuit generates the select signal Sse. The circuit for controlling a cache memory which is divided into a plurality of banks enables the writing of data in the cache in every cycle.

Abstract: A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is .UPSILON., into consecutive N-digit sets (N is a natural number equal to or less than M) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.1 according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i (Z.sub.gi is the value of an ith set (i represents natural numbers equal to or greater than a predetermined number)) and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i and a selection circuit for selecting one of one or more numbers having the same format as that of the intermediate carry C.sub.i corresponding to the ith set and for outputting the selected number to the recoding circuit as the intermediate carry C.sub.i-1 corresponding to the (i-1)th set.

Abstract: A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is .UPSILON., into consecutive N-digit sets (N is a natural number equal to or less than M) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.i according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i (Z.sub.gi is the value of an ith set (i represents natural numbers equal to or greater than a predetermined number)) and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i and a selection circuit for selecting one of one or more numbers having the same format as that of the intermediate carry C.sub.i corresponding to the ith set and for outputting the selected number to the recoding circuit as the intermediate carry C.sub.i-1 corresponding to the (i-1)th set.

Abstract: A floating point addition/subtraction apparatus is internally provided with a leading one anticipator having redundant binary numeral generators, intermediate-carry/intermediate-sum generators, and scan-value generators. Each of the redundant binary numeral generators performs a subtraction with respect to two binary operands, a binary minuend and a binary subtrahend, to generate a redundant binary numeral Zsd having "-1", "0" or "1" at each digit thereof. Each of the intermediate-carry/intermediate-sum generators generates an intermediate carry C.sub.k and an intermediate sum S.sub.k in accordance with Zsd.sub.k =2C.sub.k +S.sub.k using a redundant binary numeral Zsd.sub.k positioned at a k.sup.th digit from a least significant digit of the redundant binary numeral Zsd and a redundant binary numeral Zsd.sub.k+1 positioned at a (k+1).sup.th digit so that C.sub.k =Zsd.sub.k when Zsd.sub.k+1 ="1" or "-1" and C.sub.k =0 when Zsd.sub.k+1 ="0".

Abstract: Disclosed is a process for preparing a polyarylene sulfide, which involves polycondensing a dihalogenated aromatic compound with a source of sulfur in an organic polar solvent while dehydrating at pressure under which polycondensation is performed. This process avoids dehydration operation of the raw materials, particularly the source of sulfur, prior to polycondensation, thereby resulting in the production of the polyarylene sulfide having a high molecular weight.

Abstract: A floating point addition-subtraction apparatus for adding or subtracting data having a floating point format including a mantissa operand, an exponent operand, and a sign operand. The operands are shifted right or left depending on operational status.

Abstract: An aromatic polyamide film having a dielectric strength of at least about 150 kv/mm which is useful as an electric insulating material. This film is obtained by casting a solution comprising poly(m-phenylene isophthalamide) or a copolymer thereof and an amide type solvent, drying the cast product to form a film having a residual solvent content of not more than about 60% by weight, immersing the film in an aqueous medium kept at not more than about 20.degree. C, and stretching the resulting wet film containing at least about 5% by weight of the aqueous medium in at least one direction to at least about 1.4 times the original dimension.