Patents by Inventor Akira Morita

Akira Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11965701
    Abstract: In a heat exchanger, an outer diameter of a plurality of heat transfer pipes is defined as Do, a wall thickness is defined as tP, an area represented by a numerical expression of a row pitch L1×a step pitch L2 is defined as A, and an area represented by a numerical expression of ((Do?2×tP)/2)2×? is defined as B, a relation of Do<5.5 mm, a relation of (0.2076×tP2?0.1480×tP+0.0545)×Do{circumflex over (?)}(?0.0021×tP2?0.0528×tP+0.0164)?B/A?(0.0219×tP2?0.0185×tP+0.0043)×ln (Do)+(1.6950×tP2+1.8455×tP+1.5416), and a relation of B/A<0.0076×tP2?0.0417×tP+0.0574 are satisfied.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: April 23, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akira Yatsuyanagi, Tsuyoshi Maeda, Akira Ishibashi, Atsushi Morita, Shin Nakamura
  • Publication number: 20240114941
    Abstract: The present invention provides a sweetener composition that can be used for food as a sugar substitute sweetener. Specifically, the sweetener composition contains rebaudioside O and rebaudioside N as active ingredients, or contains at least one of rebaudioside D and rebaudioside M and at least one of rebaudioside O and rebaudioside N as active ingredients. In addition, the sweetener composition is used in combination with an additional sweetener.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Inventors: Toyoshige Morita, Akira Takada
  • Publication number: 20240118040
    Abstract: A heat exchanger includes: a first heat exchanger configured to transfer heat between air and refrigerant; and a second heat exchanger provided in series with the first heat exchanger in a first direction that is a flow direction of the air, and configured to transfer heat between the air and the refrigerant. The first heat exchanger includes first heat transfer tubes through which the refrigerant flows, which are spaced apart from each other in a second direction intersecting the first direction, and each of which has a tube axis extending in a third direction intersecting the first and second directions. The second heat exchanger includes: second heat transfer tubes though which the refrigerant flows, which are spaced apart from each other in the second direction, and each of which has a tube axis extending in the third direction; and a corrugated fin provided between the second heat transfer tubes.
    Type: Application
    Filed: April 20, 2021
    Publication date: April 11, 2024
    Inventors: Shin NAKAMURA, Tsuyoshi MAEDA, Akira YATSUYANAGI, Atsushi MORITA, Akira ISHIBASHI
  • Publication number: 20240102520
    Abstract: To provide a cam clutch unit that is easy to handle before assembly, with its components prevented from lifting or detachment, and that allows production with fewer machining steps and a lower level of difficulty, while also enabling unit thickness reduction. The cam clutch unit of the present invention includes: a plurality of cams arranged between an inner race and an outer race; a cage ring having a plurality of pocket portions that restrict relative circumferential movements of the cams; and an annular spring that biases the cams. The cams have an engagement step adapted to engage with the spring on one axial end face. The cage ring has a plurality of hook portions that restrict an axial movement of the annular spring. The hook portions have a pressing part that allows the spring to press the cams towards the other axial end.
    Type: Application
    Filed: July 14, 2023
    Publication date: March 28, 2024
    Applicant: TSUBAKIMOTO CHAIN CO.
    Inventors: Akira Morita, Hirokazu Tsuneda, Yuji Kurematsu
  • Publication number: 20230410763
    Abstract: A driver includes a first driving circuit and a second driving circuit. The second driving circuit includes a computation amplifier, an output capacitor, a first feedback capacitor, and a second feedback capacitor. The computation amplifier is composed of a transistor with a breakdown voltage lower than the breakdown voltage of a transistor making up the first driving circuit. The output capacitor is disposed between an output node of the computation amplifier and the signal supply line. The first feedback capacitor is disposed between an inverting input node of the computation amplifier and the signal supply line. One end of the second feedback capacitor is coupled to the inverting input node of the computation amplifier.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 21, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Akira MORITA, Chihiro Shin
  • Publication number: 20230410762
    Abstract: A driver includes a first driving circuit and a second driving circuit. The second driving circuit includes a computation amplifier made up of a transistor with a breakdown voltage lower than a breakdown voltage of a transistor making up the first driving circuit, an output capacitor disposed between an output node of the computation amplifier and a signal supply line, and a first feedback capacitor disposed between an inverting input node of the computation amplifier and the signal supply line. The second driving circuit includes first to m-th voltage outputting capacitors including one end coupled to the inverting input node of the computation amplifier, and first to m-th voltage output circuits configured to output a voltage based on the gradation data to the other end of the first to m-th voltage outputting capacitors.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 21, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Akira MORITA, Ryota BANSHO
  • Publication number: 20230410764
    Abstract: A driver includes a first driving circuit and a second driving circuit. The second driving circuit includes a computation amplifier, an output capacitor, a first feedback capacitor, and a second feedback capacitor. One end of the output capacitor is coupled to an output node of the computation amplifier, and the other end is coupled to the signal supply line. One end of the first feedback capacitor is coupled to an inverting input node of the computation amplifier, and the other end is coupled to the signal supply line. One end of the second feedback capacitor is coupled to the inverting input node of the computation amplifier, and the other end is coupled to a predetermined potential node. At least one of the first feedback capacitor and the second feedback capacitor is a capacitor with a variable capacitance value.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 21, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Akira MORITA, Ryota BANSHO
  • Publication number: 20230317025
    Abstract: A driver includes a data voltage output terminal electrically coupled to a data line through a data line switch of an electro-optical panel, a capacitor driving circuit configured to output first to nth capacitor driving voltages corresponding to gradation data to first to nth capacitor driving nodes, a capacitor circuit including first to nth capacitors provided between an output node and the first to nth capacitor driving nodes, a processing circuit configured to calculate an excess/deficient charge amount of the output node when the data line switch is turned on, and a charge compensation circuit configured to inject into the output node or discharge from the output node a compensation charge based on the excess/deficient charge amount calculated by the processing circuit, by using a charge compensation capacitor circuit.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 5, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Akira MORITA, Chihiro SHIN
  • Publication number: 20230306923
    Abstract: A driver includes a data voltage output terminal, a capacitor drive circuit that outputs each of first to n-th capacitor drive voltages corresponding to gradation data to a respective one of first to n-th capacitor driving nodes, a capacitor circuit including first to n-th capacitors each provided between an output node and a respective one of the first to n-th capacitor driving nodes, a processing circuit that generates a correction signal for correcting a voltage difference between an output voltage and a target voltage corresponding to the gradation data, and a correction circuit that corrects the voltage difference with a correction voltage corresponding to the voltage difference by injecting a charge corresponding to the correction signal into the output node or discharging the charge from the output node by using the correction capacitor circuit.
    Type: Application
    Filed: March 28, 2023
    Publication date: September 28, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Ryota BANSHO, Akira MORITA
  • Patent number: 11768255
    Abstract: An integrated circuit includes a capacitance element to be tested and a test circuit in the same semiconductor substrate, the test circuit includes a capacitance element for testing, and a comparison circuit for comparing a voltage of a node with a voltage of a signal, electrically connects another end of the capacitance element to be tested to the node, applies the voltage of the signal to the node in a first period, changes the voltage of the node based on a capacitance ratio of the capacitance element to be tested and the capacitance element for testing, and tests a capacity size of the capacitance element to be tested based on a comparison result of the comparison circuit in a second period after the first period.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: September 26, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Akira Morita, Shinya Ukai
  • Publication number: 20230115992
    Abstract: The problem of providing an oil and fat for chocolate products and a chocolate product each having oil and fat migration/blooming resistance and post-tempering thickening resistance can be solved by an oil and fat for chocolate products according to the present invention, an oil or fat for chocolate products according to the present invention which is obtained by mixing an oil and fat mainly composed of a StOSt triglyceride with a low-melting-point fraction of palm oil that serving as a liquid oil component and further contains a specific amount of an OStO component.
    Type: Application
    Filed: January 28, 2021
    Publication date: April 13, 2023
    Applicant: FUJI OIL HOLDINGS INC.
    Inventor: Akira MORITA
  • Publication number: 20230060352
    Abstract: Systems and methods for improved fluid dispensing process control using a machine learning tool are disclosed. In an example method, successive portions of viscous fluid are dispensed by a dispensing device according to operating parameters to train a machine learning tool to associate defect classifications with images of dispensed portions and/or operating parameters associated with dispensing the dispensed portions. The trained machine learning tool is then used in a closed loop fashion in production to detect and correct for defects associated with the dispensed portions to improve quality and production efficiency.
    Type: Application
    Filed: February 19, 2021
    Publication date: March 2, 2023
    Inventors: Alan R. LEWIS, Cutler CROWELL, III, Michael GORMAN, Akira MORITA
  • Publication number: 20220284868
    Abstract: A display system includes a data processing unit and a liquid crystal panel. The data processing unit partitions display data pixels in one frame into, for example, blocks of four pixels in two rows×two columns, performs predetermined processing on display data of four display data pixels, and transmits processing data with an amount of data of 1?4 pixels to the liquid crystal panel in four subframes. Panel pixels of the liquid crystal panel are partitioned into blocks of four pixels in two rows×two columns, data signals based on processing data are provided to four panel pixels included in one block in a subframe f1 among the four subframes, and of the four subframes, in subframes f2 to f4, data signals based on the processing data are provided in a predetermined order to three of the panel pixels included in the one block.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 8, 2022
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kota MOCHIZUKI, Akira MORITA
  • Publication number: 20220236340
    Abstract: An integrated circuit includes a capacitance element to be tested and a test circuit in the same semiconductor substrate, the test circuit includes a capacitance element for testing, and a comparison circuit for comparing a voltage of a node with a voltage of a signal, electrically connects another end of the capacitance element to be tested to the node, applies the voltage of the signal to the node in a first period, changes the voltage of the node based on a capacitance ratio of the capacitance element to be tested and the capacitance element for testing, and tests a capacity size of the capacitance element to be tested based on a comparison result of the comparison circuit in a second period after the first period.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 28, 2022
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Akira MORITA, Shinya UKAI
  • Patent number: 11302232
    Abstract: A circuit device configured to drive an electro-optical panel including a demultiplexer provided between a first to n-th data lines, n being an integer of three or greater, and a data signal supply line, includes a data line driving circuit configured to output a data signal to the data signal supply line, and a processing circuit configured to set a selection order, by the demultiplexer, of the first to n-th data lines. When an i-th data line, i being an integer of 1 to n, is selected j-th, j being an integer of 1 to n, in the first selection order, the processing circuit sets a second selection order using random number information so as to prohibit the i-th data line from being selected j-th in the second selection order.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 12, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Fukukai Ryu, Akira Morita
  • Publication number: 20220087361
    Abstract: A rubber foam for a shoe sole is composed of a rubber composition for foaming containing a rubber composition and a foaming agent, the rubber foam having (i) a loss factor tan ? (24° C.) at a frequency of 10 Hz and 24° C. that is 0.07 or less and (ii) an absolute value of a slope of a change in loss factor tan ? with temperature between a loss factor tan ? (?15° C.) at the frequency of 10 Hz and ?15° C. and the loss factor tan ? (24° C.) at the frequency of 10 Hz and 24° C., as calculated by the following equation, that is 0.002 or less: the absolute value of the slope of the change in tan ? with temperature=|[tan ? (?15° C.)?tan ? (24° C.)]/39|.
    Type: Application
    Filed: June 3, 2021
    Publication date: March 24, 2022
    Inventors: Mitsuru Sato, Akira MORITA, Naoya HIGUCHI
  • Patent number: 11263944
    Abstract: A circuit device includes a transfer gate and a control circuit. The transfer gate includes a P-type transistor and an N-type transistor. The control circuit sets, as a first value, a transistor size ratio that is a ratio of a size of the P-type transistor to a size of the N-type transistor when a voltage of an input signal to the transfer gate is in a first voltage range at a timing at which the transfer gate is turned off. The control circuit sets the transistor size ratio as a second value greater than the first value when a voltage of the input signal is in a second voltage range lower than that in the first voltage range at a timing at which the transfer gate is turned off.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 1, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Akira Morita
  • Patent number: 11132933
    Abstract: A circuit device includes a first input terminal, a second input terminal, a reception circuit including a non-inverted input terminal and an inverted input terminal, a first signal line electrically coupling a non-inverted input terminal of the reception circuit and the first input terminal and having a first coupling node and a second coupling node, a second signal line electrically coupling an inverted input terminal of the reception circuit and the second input terminal and having a third coupling node and fourth coupling node, a first variable capacitance circuit having an end coupled to the first coupling node and another end coupled to the second coupling node, and a second variable capacitance circuit having an end coupled to the third coupling node and another end coupled to the fourth coupling node.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 28, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Jun Ishida, Akira Morita
  • Patent number: 11094274
    Abstract: A circuit device includes a transfer gate, a charge compensation circuit, and a control circuit. The control circuit controls the charge compensation circuit. The charge compensation circuit discharges charge from an output node of the transfer gate when a voltage of an input signal to the transfer gate is in a first voltage range at a timing at which the transfer gate is turned off. The charge compensation circuit injects charge into the output node of the transfer gate when a voltage of the input signal to the transfer gate is in a second voltage range lower than that in the first voltage range at a timing at which the transfer gate is turned off.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 17, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Akira Morita
  • Publication number: 20210225241
    Abstract: A circuit device configured to drive an electro-optical panel including a demultiplexer provided between a first to n-th data lines, n being an integer of three or greater, and a data signal supply line, includes a data line driving circuit configured to output a data signal to the data signal supply line, and a processing circuit configured to set a selection order, by the demultiplexer, of the first to n-th data lines. When an i-th data line, i being an integer of 1 to n, is selected j-th, j being an integer of 1 to n, in the first selection order, the processing circuit sets a second selection order using random number information so as to prohibit the i-th data line from being selected j-th in the second selection order.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 22, 2021
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Fukukai RYU, Akira MORITA