Abstract: A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

Abstract: In an LSI, a decoding section decodes an ID signal received externally and outputs the decoded signal. A fuse circuit writes the value represented by the decoded signal therein when an operation setting signal is active, and holds the written value when the operation setting signal is inactive. An ID RAM stores the value held in the fuse circuit as the ID. This enables installation of IDs of various values in LSIs only by changing the value of the ID signal.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: In an LSI, a decoding section decodes an ID signal received externally and outputs the decoded signal. A fuse circuit writes the value represented by the decoded signal therein when an operation setting signal is active, and holds the written value when the operation setting signal is inactive. An ID RAM stores the value held in the fuse circuit as the ID. This enables installation of IDs of various values in LSIs only by changing the value of the ID signal.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.

Abstract: The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.

Abstract: A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

Abstract: Information about an exclusive operation among a plurality of blocks and interconnection information about a sharable resource within each of these blocks are defined. Based on the sharable resource information and the inter-block exclusive operation information, a resource sharable among the blocks is extracted. Module specifications, in which information about interfaces, power dissipation, operation models and top-level hierarchy interconnection is stored, exclusive operation information describing an exclusive operation rule among the blocks, and prioritized function information used for preventing respective functions from being enabled at the same time are input to an generator, which is an automatic generating tool.

Abstract: The method for designing an integrated circuit device of the present invention includes the steps of: obtaining the number of operations by a functional simulation; determining a specification model based on the number of operations; determining an behavioral model corresponding to the specification model based on the number of operations per cycle required; determining a RTL model corresponding to the behavioral model based on the number of operations per cycle required; and obtaining design data corresponding to the RTL model for implementing the function.

Abstract: The method for designing an integrated circuit device of the present invention includes the steps of: obtaining the number of operations by a functional simulation; determining a specification model based on the number of operations; determining an behavioral model corresponding to the specification model based on the number of operations per cycle required; determining a RTL model corresponding to the behavioral model based on the number of operations per cycle required; and obtaining design data corresponding to the RTL model for implementing the function.

Abstract: Architecture design (AD), architecture floorplanning (AF), and transaction analysis (TA) are performed before transaction-analysis-based floorplanning (TF). Then, area estimation (CE) is performed on functional parts and connections before area-based floorplanning (CF) and area optimization (CO) are performed, and whether or not the area specifications area satisfied or not is validated (CR). Besides, power consumption estimation (PE) is performed to check whether or not the power consumption specifications are satisfied (PR). In the case of taking a parallelization approach to realize lower power consumption, parallelization design (PD) is performed. After the power consumption specifications are satisfied, power supply wiring/floorplanning is performed.

Abstract: In an LSI, a decoding section decodes an ID signal received externally and outputs the decoded signal. A fuse circuit writes the value represented by the decoded signal therein when an operation setting signal is active, and holds the written value when the operation setting signal is inactive. An ID RAM stores the value held in the fuse circuit as the ID. This enables installation of IDs of various values in LSIs only by changing the value of the ID signal.

Abstract: In an integrated circuit device, when a net having many toggle counts exists in a circuit including blocks each having function modules, the circuit is changed to an equivalent circuit where the net is included inside a block. In the circuit, when the toggle counts of a function module in a block are especially many, a plurality of parallel blocks is provided in place of the block. When a plurality of pins of a block can be exchanged without changing the output value although the internal toggle counts of the block changes, the input pins are exchanged so that the internal toggle counts are less. Objects to be connected via a net having many toggle counts are given priority to be placed closer to each other in the floor plan.

Abstract: Information about an exclusive operation among a plurality of blocks and interconnection information about a sharable resource within each of these blocks are defined. Based on the sharable resource information and the inter-block exclusive operation information, a resource sharable among the blocks is extracted. Module specifications, in which information about interfaces, power dissipation, operation models and top-level hierarchy interconnection is stored, exclusive operation information describing an exclusive operation rule among the blocks, and prioritized function information used for preventing respective functions from being enabled at the same time are input to an generator, which is an automatic generating tool.

Abstract: An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

Abstract: Information about an exclusive operation among a plurality of blocks and interconnection information about a sharable resource within each of these blocks are defined. Based on the sharable resource information and the inter-block exclusive operation information, a resource sharable among the blocks is extracted. Module specifications, in which information about interfaces, power dissipation, operation models and top-level hierarchy interconnection is stored, exclusive operation information describing an exclusive operation rule among the blocks, and prioritized function information used for preventing respective functions from being enabled at the same time are input to an generator, which is an automatic generating tool.

Abstract: The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.

Abstract: Architecture design (AD), architecture floorplanning (AF), and transaction analysis (TA) are performed before transaction-analysis-based floorplanning (TF). Then, area estimation (CE) is performed on functional parts and connections before area-based floorplanning (CF) and area optimization (CO) are performed, and whether or not the area specifications area satisfied or not is validated (CR). Besides, power consumption estimation (PE) is performed to check whether or not the power consumption specifications are satisfied (PR). In the case of taking a parallelization approach to realize lower power consumption, parallelization design (PD) is performed. After the power consumption specifications are satisfied, power supply wiring/floorplanning is performed.