Abstract: A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

Abstract: A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

Abstract: Three blocks cascaded to one another in an LSI, namely, an input module, a macro module and an output module, are independently tested. A first test circuit is formed with a first multiplexer interposed between the macro module and the output module, and a second multiplexer and a first control register interposed between the input module and the macro module. A second test circuit is similarly formed with third and fourth multiplexers and a second control register. A test input signal of a plurality of bits is supplied to the first multiplexer, and a latched signal of the first control register is supplied to the third multiplexer, thereby allowing a latched signal of the second control register to be output as a test output signal for observation. Thus, testing techniques requiring a small additional circuit and a small number of additional wires for the test can be provided.

Abstract: Three blocks cascaded to one another in an LSI, namely, an input module, a macro module and an output module, are independently tested. A first test circuit is formed with a first multiplexer interposed between the macro module and the output module, and a second multiplexer and a first control register interposed between the input module and the macro module. A second test circuit is similarly formed with third and fourth multiplexers and a second control register. A test input signal of a plurality of bits is supplied to the first multiplexer, and a latched signal of the first control register is supplied to the third multiplexer, thereby allowing a latched signal of the second control register to be output as a test output signal for observation. Thus, testing techniques requiring a small additional circuit and a small number of additional wires for the test can be provided.

Abstract: This invention is intended for a semiconductor integrated circuit with scan logical blocks wherein scan flip-flops are used for interblock signal communication. A testing sequence is generated to detect a fault in a target scan logical block. First, a block testing sequence, which is a testing sequence to the scan logical block as a single circuit, is generated. If signal inversion occurs in a scan chain that runs through the scan logical block, data that is inputted to or outputted from the scan logical block via such a scan chain is inverted. Patterns equal in number to the semiconductor integrated circuit's structure are placed in front of and behind a shift-in pattern and a shift-out pattern in the block testing sequence, to convert the block testing sequence into a testing sequence for the entire semiconductor integrated circuit. Upon completion of all the testing sequence generation with respect to the scan logical blocks, the generated testing sequences are merged.

Abstract: A method for generating a test sequence for a fault in a sequential circuit to provide high fault coverage. In one embodiment (FIG. 1), a circuit state, which a system fails to justify, is stored as an illegal state in a step 107. In a step 103, a target fault is selected. In a step 104, the system performs its fault propagation processing to generate a test sequence and propagate the target fault from a fault location to any external output pin in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation. In a step 105, the system performs its state initialization processing to generate a test sequence and transfer the state of the circuit from its initial state to a state when the fault was sensitized in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation.

Abstract: In an apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit wherein logical values of bits of the plurality of storage elements being represented by a state, first external input values are generated so that a transition process is performed from a second state of the plurality of storage elements to a first state thereof, and second external input values are generated so hat a transition process is performed from a third state of the plurality of storage elements to the first state thereof. Thereafter, third external input values are generated so that a transition process is performed from a fourth state of the plurality of storage elements to the first state thereof. After setting the fourth state as the first state, name data of storage elements corresponding to bits of different states between the second and third states are stored in a storage unit.

Abstract: An apparatus for and method of performing automatic test pattern generation for a digital circuit specified registers when the process of automatic test pattern generation for one or more faults is aborted which allow detection of circuit faults by scanning the specified registers. The scan request count of the specified registers is updated, and registers having a scan request count greater than the scan request count limit are recognized as critical registers. Automatic test pattern generation is performed while regarding the critical registers as scan registers.

Abstract: An efficient method of generating test sequences for sequential circuits is disclosed. This method generates a test sequence for a combinational circuit which includes an object fault, examines memory elements where a resulting state (other than "don't care") has been set as a result of the fault. This is followed by fault propagation and state justification. In the event that, due to such factors as limitations in computing time, generation of test sequence was aborted during fault propagation or state justification, the states of the memory elements are provided for determining which memory element should be scanned to detect the fault. In another embodiment an assumed fault from previous processing has been propagated to a memory element and, thus, to a pseudo primary input terminal. The results of the previous processing are used to propagate the fault to a primary output terminal or to another memory element and, thus, to another pseudo primary output terminal.