Patents by Inventor Akira Ohtani

Akira Ohtani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10414884
    Abstract: A carbon fiber bundle for resin reinforcement, wherein there are adhered by 0.1-5.0 mass % to a carbon fiber bundle in which multiple lengths of filament are bundled, a mixture created by mixing an organic polymer (A) having a mass-average molecular weight of 10000 or more and an organic compound (B) the thermal reduction rate specified in claim 1 of which is 5 mass % or more or an organic compound (B) the thermal reduction rate specified in claim 2 of which is 0.8 mass % or more, the amount of the organic polymer (A) adhered being 0.1 mass % or more.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 17, 2019
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Tadashi Ohtani, Atsushi Takahashi, Saki Fujita, Akira Harada
  • Patent number: 10319757
    Abstract: A photoelectric conversion device includes a photoelectric conversion portion in a silicon layer having a light-receiving surface. The silicon layer includes a P-type impurity region including a base portion having an atomic boron concentration Ba that is the highest of the portions opposite the light-receiving surface with respect to a charge accumulation region and an atomic oxygen concentration Oa, and a deep portion located opposite the charge accumulation region in the depth direction with respect to the base portion and having an atomic boron concentration Bb and an atomic oxygen concentration Ob. The impurity region satisfies Ba×Oa2<Bb×Ob2.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 11, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Ohtani, Tasuku Kaneda
  • Patent number: 10321075
    Abstract: Provided is an imaging apparatus including a pixel array in which a plurality of pixels are arranged in a matrix, each of the pixels comprising a photoelectric conversion portion. The pixel array includes a first pixel configured to output an imaging signal in accordance with an incident light and a second pixel configured to output a correction signal used for correcting the imaging signal. The second pixel outputs the correction signal after performing a first reset performed in a state where a first bias voltage is applied to the photoelectric conversion portion of the second pixel and a second reset performed in a state where a second bias voltage that is different from the first bias voltage is applied to the photoelectric conversion portion.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 11, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tasuku Kaneda, Kei Ochiai, Akira Ohtani
  • Publication number: 20190096946
    Abstract: An imaging apparatus includes a substrate including a photoelectric conversion portion; and a silicon nitride layer arranged to cover at least a portion of the photoelectric conversion portion. The silicon nitride layer contains chlorine. An N/Si composition ratio in the silicon nitride layer is not less than 1.00 and is less than 1.33.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 28, 2019
    Inventors: Katsunori Hirota, Keiichi Sasaki, Tsutomu Tange, Yoshiei Tanaka, Akira Ohtani
  • Publication number: 20180139400
    Abstract: Provided is an imaging apparatus including a pixel array in which a plurality of pixels are arranged in a matrix, each of the pixels comprising a photoelectric conversion portion. The pixel array includes a first pixel configured to output an imaging signal in accordance with an incident light and a second pixel configured to output a correction signal used for correcting the imaging signal. The second pixel outputs the correction signal after performing a first reset performed in a state where a first bias voltage is applied to the photoelectric conversion portion of the second pixel and a second reset performed in a state where a second bias voltage that is different from the first bias voltage is applied to the photoelectric conversion portion.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 17, 2018
    Inventors: Tasuku Kaneda, Kei Ochiai, Akira Ohtani
  • Publication number: 20180061872
    Abstract: A photoelectric conversion device includes a photoelectric conversion portion in a silicon layer having a light-receiving surface. The silicon layer includes a P-type impurity region including a base portion having an atomic boron concentration Ba that is the highest of the portions opposite the light-receiving surface with respect to a charge accumulation region and an atomic oxygen concentration Oa, and a deep portion located opposite the charge accumulation region in the depth direction with respect to the base portion and having an atomic boron concentration Bb and an atomic oxygen concentration Ob. The impurity region satisfies Ba×Oa2<Bb×Ob2.
    Type: Application
    Filed: August 22, 2017
    Publication date: March 1, 2018
    Inventors: Akira Ohtani, Tasuku Kaneda
  • Patent number: 9554069
    Abstract: A solid-state imaging apparatus includes: a photoelectric conversion unit configured to convert light into an electric charge; a floating diffusion region configured to convert the electric charge into a voltage; a transfer transistor configured to transfer the electric charge from the photoelectric conversion unit to the floating diffusion region; and a transfer transistor driving circuit configured to control a gate potential of the transfer transistor, wherein the transfer transistor driving circuit controls the gate potential so as to be changed in at least two changing rates during a period of transition from the ON state to the OFF state of the transfer transistor, and the second changing rate out of the two changing rates is higher than the first changing rate.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 24, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shinichiro Shimizu, Akira Ohtani, Masaru Fujimura
  • Publication number: 20150070554
    Abstract: A solid-state imaging apparatus includes: a photoelectric conversion unit configured to convert light into an electric charge; a floating diffusion region configured to convert the electric charge into a voltage; a transfer transistor configured to transfer the electric charge from the photoelectric conversion unit to the floating diffusion region; and a transfer transistor driving circuit configured to control a gate potential of the transfer transistor, wherein the transfer transistor driving circuit controls the gate potential so as to be changed in at least two changing rates during a period of transition from the ON state to the OFF state of the transfer transistor, and the second changing rate out of the two changing rates is higher than the first changing rate.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 12, 2015
    Inventors: Shinichiro Shimizu, Akira Ohtani, Masaru Fujimura
  • Patent number: 8878261
    Abstract: A semiconductor device comprising a MOS transistor provided in a semiconductor region, wherein a source region and a drain region of the MOS transistor have a first conductivity type, the source region includes a first region including an upper portion of a boundary portion between the source region and a channel region of the MOS transistor, and a second region including an lower portion of the boundary portion, and the first region contains an impurity having a second conductivity type different from the first conductivity type, in an amount larger than that in the second region.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: November 4, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Akira Ohtani
  • Publication number: 20130321660
    Abstract: A semiconductor device comprising a MOS transistor provided in a semiconductor region, wherein a source region and a drain region of the MOS transistor have a first conductivity type, the source region includes a first region including an upper portion of a boundary portion between the source region and a channel region of the MOS transistor, and a second region including an lower portion of the boundary portion, and the first region contains an impurity having a second conductivity type different from the first conductivity type, in an amount larger than that in the second region.
    Type: Application
    Filed: May 8, 2013
    Publication date: December 5, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Akira Ohtani
  • Patent number: 8501520
    Abstract: A manufacturing method for a solid-state image sensor, the method comprises the steps of: forming a charge storage region in a photoelectric converting unit by implanting a semiconductor substrate with ions of an impurity of a first conductivity type, using a first mask; heating the semiconductor substrate at a temperature of no less than 800° C. and no more than 1200° C. through RTA (Rapid Thermal Annealing); forming a surface region of the charge storage region by implanting the semiconductor substrate with ions of an impurity of a second conductivity type, using a second a mask; heating the semiconductor substrate at a temperature of no less than 800° C. and no more than 1200° C. through RTA (Rapid Thermal Annealing); and forming an antireflection film that covers the photoelectric converting unit at a temperature of less than 800° C., after the step of forming the surface region, in this order.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: August 6, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsunori Hirota, Akira Ohtani, Kazuaki Tashiro, Yusuke Onuki, Takanori Watanabe, Takeshi Ichikawa
  • Patent number: 8482646
    Abstract: An image sensing device comprises a pixel array, and a peripheral circuit, a column selecting circuit, and a readout, wherein each pixel includes a photodiode, a floating diffusion, a transfer PMOS transistor to the floating diffusion, an amplifier PMOS transistor, and a reset PMOS transistor, the amplifier PMOS transistor has a gate which is formed by an n-type conductive pattern, and is isolated by a first element isolation region and an n-type impurity region which covers at least a lower portion of the first element isolation region, and each PMOS transistor included in the column selecting circuit has a gate which is formed by a p-type conductive pattern and is isolated by a second element isolation region, and an n-type impurity concentration in a region adjacent to a lower portion of the second element isolation region is lower than that in the n-type impurity region.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: July 9, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takanori Watanabe, Mineo Shimotsusa, Takeshi Ichikawa, Hajime Ikeda, Yasuhiro Sekine, Akira Ohtani, Takeshi Kojima
  • Patent number: 8053272
    Abstract: A method of fabricating a semiconductor device, comprises steps of forming a common contact hole for a first conductivity-type region and a second conductivity-type region, implanting an impurity in at least one of the first conductivity-type region and the second conductivity-type region, and forming a shared contact plug by filling an electrical conducting material in the contact hole, wherein in the implanting step, an impurity is implanted in at least one of the first conductivity-type region and the second conductivity-type region such that the first conductivity-type region and the shared contact plug are brought into ohmic contact with each other, and the second conductivity-type region and the shared contact plug are brought into ohmic contact with each other.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: November 8, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Ohtani, Takanori Watanabe, Takeshi Ichikawa
  • Publication number: 20110242388
    Abstract: An image sensing device comprises a pixel array, and a peripheral circuit, a column selecting circuit, and a readout, wherein each pixel includes a photodiode, a floating diffusion, a transfer PMOS transistor to the floating diffusion, an amplifier PMOS transistor, and a reset PMOS transistor, the amplifier PMOS transistor has a gate which is formed by an n-type conductive pattern, and is isolated by a first element isolation region and an n-type impurity region which covers at least a lower portion of the first element isolation region, and each PMOS transistor included in the column selecting circuit has a gate which is formed by a p-type conductive pattern and is isolated by a second element isolation region, and an n-type impurity concentration in a region adjacent to a lower portion of the second element isolation region is lower than that in the n-type impurity region.
    Type: Application
    Filed: January 20, 2010
    Publication date: October 6, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Takanori Watanabe, Mineo Shimotsusa, Takeshi Ichikawa, Hajime Ikeda, Yasuhiro Sekine, Akira Ohtani, Takeshi Kojima
  • Publication number: 20100203667
    Abstract: A manufacturing method for a solid-state image sensor, the method comprises the steps of: forming a charge storage region in a photoelectric converting unit by implanting a semiconductor substrate with ions of an impurity of a first conductivity type, using a first mask; heating the semiconductor substrate at a temperature of no less than 800° C. and no more than 1200° C. through RTA (Rapid Thermal Annealing); forming a surface region of the charge storage region by implanting the semiconductor substrate with ions of an impurity of a second conductivity type, using a second a mask; heating the semiconductor substrate at a temperature of no less than 800° C. and no more than 1200° C. through RTA (Rapid Thermal Annealing); and forming an antireflection film that covers the photoelectric converting unit at a temperature of less than 800° C., after the step of forming the surface region, in this order.
    Type: Application
    Filed: February 1, 2010
    Publication date: August 12, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Katsunori Hirota, Akira Ohtani, Kazuaki Tashiro, Yusuke Onuki, Takanori Watanabe, Takeshi Ichikawa
  • Publication number: 20100203670
    Abstract: A method of fabricating a semiconductor device, comprises steps of forming a common contact hole for a first conductivity-type region and a second conductivity-type region, implanting an impurity in at least one of the first conductivity-type region and the second conductivity-type region, and forming a shared contact plug by filling an electrical conducting material in the contact hole, wherein in the implanting step, an impurity is implanted in at least one of the first conductivity-type region and the second conductivity-type region such that the first conductivity-type region and the shared contact plug are brought into ohmic contact with each other, and the second conductivity-type region and the shared contact plug are brought into ohmic contact with each other.
    Type: Application
    Filed: January 25, 2010
    Publication date: August 12, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Akira Ohtani, Takanori Watanabe, Takeshi Ichikawa
  • Patent number: 7537711
    Abstract: The invention provides a fuel cell which comprises a solid polymer electrolyte sandwiched between a cathode to which an oxidizing agent gas is supplied and an anode to which a reducing agent gas is supplied, wherein at least one of the electrodes has an electroconductive organic polymer which has an oxidation-reduction function as an electrode catalyst. The invention further provides a fuel cell in which the electrode catalyst comprises a mixture of an electroconductive organic polymer and an inorganic oxidation-reduction catalyst, and has a higher output power.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: May 26, 2009
    Assignee: Nitto Denko Corporation
    Inventors: Masao Abe, Akira Ohtani, Kuniaki Ishibashi
  • Patent number: 7510673
    Abstract: For mounting on a substrate by using an electroconductive adhesive, an electroconductive paste for forming an external electrode which has improved moisture resistance and which is resistant to occurrence of external-electrode peeling, as well as a ceramic electronic component including the electroconductive paste are provided. The electroconductive paste includes a base-metal electroconductive powder, first glass frit, and an organic vehicle, wherein the first glass frit has a B2O3 content of 10 to 20 percent by mole, a SiO2 content of 50 to 65 percent by mole, an alkali metal oxide content of 10 to 20 percent by mole, a ZnO content of 1 to 5 percent by mole, a TiO2 content of 1 to 5 percent by mole, a ZrO2 content of 1 to 5 percent by mole, and an Al2O3 content of 1 to 5 percent by mole.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: March 31, 2009
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Akira Ohtani, Yuji Ukuma
  • Patent number: 7468219
    Abstract: The invention provides a fuel cell which comprises a solid polymer electrolyte sandwiched between a cathode to which an oxidizing agent gas is supplied and an anode to which a reducing agent gas is supplied, wherein at least one of the electrodes has an electroconductive organic polymer which has an oxidation-reduction function as an electrode catalyst. The invention further provides a fuel cell in which the electrode catalyst comprises a mixture of an electroconductive organic polymer and an inorganic oxidation-reduction catalyst, and has a higher output power.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: December 23, 2008
    Assignee: Nitto Denko Corporation
    Inventors: Masao Abe, Akira Ohtani, Kuniaki Ishibashi
  • Patent number: 7393715
    Abstract: In an image pickup device, a step of forming an embedded plug includes a step of forming a connecting hole in the insulation film in which the embedded plug is to be formed, a metal layer deposition step of depositing a metal layer on the insulation film in which the connecting hole is formed, thereby covering an interior of the connecting hole and at least a part of an upper surface of the insulation film in a laminating direction thereof, and a metal layer removing step of polishing the upper surface of the insulation film on which the metal layer is deposited thereby removing the metal layer except for the interior of the connecting hole, an etch-back method performed on the embedded plug in at least an insulation film, and a chemical mechanical polishing method performed on the embedded plug in another insulation film.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: July 1, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koichi Tazoe, Sakae Hashimoto, Akira Ohtani, Hiroshi Yuzurihara