Patents by Inventor Akira Ohtani
Akira Ohtani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11094733Abstract: A semiconductor device has a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor is arranged in an active region of a semiconductor substrate, and a gate electrode and the active region overlap with each other in a plan view and also have a portion located between the source and the drain of the first transistor of the semiconductor substrate. In the channel width direction, an impurity concentration of the second conductivity type is higher at the end than on the center side of the portion.Type: GrantFiled: October 14, 2019Date of Patent: August 17, 2021Assignee: CANON KABUSHIKI KAISHAInventors: Akira Oseto, Tatsunori Kato, Ryunosuke Ishii, Takanori Watanabe, Atsushi Suzuki, Koichiro Iwata, Kazuo Yamazaki, Hideaki Takada, Akira Ohtani
-
Publication number: 20200295063Abstract: A photoelectric conversion apparatus includes: a substrate having a photoelectric conversion portion; a gate electrode of a transfer transistor provided on the substrate and configured to transfer charges generated by the photoelectric conversion portion; a first film; a second film provided on the first film; and a contact plug being in contact with the second film and connected to the transfer transistor.Type: ApplicationFiled: March 6, 2020Publication date: September 17, 2020Inventors: Yoshiyuki Nakagawa, Takafumi Miki, Akira Ohtani, Masashi Kusukawa
-
Patent number: 10777596Abstract: An imaging apparatus includes a substrate including a photoelectric conversion portion; and a silicon nitride layer arranged to cover at least a portion of the photoelectric conversion portion. The silicon nitride layer contains chlorine. An N/Si composition ratio in the silicon nitride layer is not less than 1.00 and is less than 1.33.Type: GrantFiled: September 21, 2018Date of Patent: September 15, 2020Assignee: CANON KABUSHIKI KAISHAInventors: Katsunori Hirota, Keiichi Sasaki, Tsutomu Tange, Yoshiei Tanaka, Akira Ohtani
-
Publication number: 20200127035Abstract: A semiconductor device has a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor is arranged in an active region of a semiconductor substrate, and a gate electrode and the active region overlap with each other in a plan view and also have a portion located between the source and the drain of the first transistor of the semiconductor substrate. In the channel width direction, an impurity concentration of the second conductivity type is higher at the end than on the center side of the portion.Type: ApplicationFiled: October 14, 2019Publication date: April 23, 2020Inventors: Akira Oseto, Tatsunori Kato, Ryunosuke Ishii, Takanori Watanabe, Atsushi Suzuki, Koichiro Iwata, Kazuo Yamazaki, Hideaki Takada, Akira Ohtani
-
Patent number: 10321075Abstract: Provided is an imaging apparatus including a pixel array in which a plurality of pixels are arranged in a matrix, each of the pixels comprising a photoelectric conversion portion. The pixel array includes a first pixel configured to output an imaging signal in accordance with an incident light and a second pixel configured to output a correction signal used for correcting the imaging signal. The second pixel outputs the correction signal after performing a first reset performed in a state where a first bias voltage is applied to the photoelectric conversion portion of the second pixel and a second reset performed in a state where a second bias voltage that is different from the first bias voltage is applied to the photoelectric conversion portion.Type: GrantFiled: October 31, 2017Date of Patent: June 11, 2019Assignee: CANON KABUSHIKI KAISHAInventors: Tasuku Kaneda, Kei Ochiai, Akira Ohtani
-
Patent number: 10319757Abstract: A photoelectric conversion device includes a photoelectric conversion portion in a silicon layer having a light-receiving surface. The silicon layer includes a P-type impurity region including a base portion having an atomic boron concentration Ba that is the highest of the portions opposite the light-receiving surface with respect to a charge accumulation region and an atomic oxygen concentration Oa, and a deep portion located opposite the charge accumulation region in the depth direction with respect to the base portion and having an atomic boron concentration Bb and an atomic oxygen concentration Ob. The impurity region satisfies Ba×Oa2<Bb×Ob2.Type: GrantFiled: August 22, 2017Date of Patent: June 11, 2019Assignee: Canon Kabushiki KaishaInventors: Akira Ohtani, Tasuku Kaneda
-
Publication number: 20190096946Abstract: An imaging apparatus includes a substrate including a photoelectric conversion portion; and a silicon nitride layer arranged to cover at least a portion of the photoelectric conversion portion. The silicon nitride layer contains chlorine. An N/Si composition ratio in the silicon nitride layer is not less than 1.00 and is less than 1.33.Type: ApplicationFiled: September 21, 2018Publication date: March 28, 2019Inventors: Katsunori Hirota, Keiichi Sasaki, Tsutomu Tange, Yoshiei Tanaka, Akira Ohtani
-
Publication number: 20180139400Abstract: Provided is an imaging apparatus including a pixel array in which a plurality of pixels are arranged in a matrix, each of the pixels comprising a photoelectric conversion portion. The pixel array includes a first pixel configured to output an imaging signal in accordance with an incident light and a second pixel configured to output a correction signal used for correcting the imaging signal. The second pixel outputs the correction signal after performing a first reset performed in a state where a first bias voltage is applied to the photoelectric conversion portion of the second pixel and a second reset performed in a state where a second bias voltage that is different from the first bias voltage is applied to the photoelectric conversion portion.Type: ApplicationFiled: October 31, 2017Publication date: May 17, 2018Inventors: Tasuku Kaneda, Kei Ochiai, Akira Ohtani
-
Publication number: 20180061872Abstract: A photoelectric conversion device includes a photoelectric conversion portion in a silicon layer having a light-receiving surface. The silicon layer includes a P-type impurity region including a base portion having an atomic boron concentration Ba that is the highest of the portions opposite the light-receiving surface with respect to a charge accumulation region and an atomic oxygen concentration Oa, and a deep portion located opposite the charge accumulation region in the depth direction with respect to the base portion and having an atomic boron concentration Bb and an atomic oxygen concentration Ob. The impurity region satisfies Ba×Oa2<Bb×Ob2.Type: ApplicationFiled: August 22, 2017Publication date: March 1, 2018Inventors: Akira Ohtani, Tasuku Kaneda
-
Patent number: 9554069Abstract: A solid-state imaging apparatus includes: a photoelectric conversion unit configured to convert light into an electric charge; a floating diffusion region configured to convert the electric charge into a voltage; a transfer transistor configured to transfer the electric charge from the photoelectric conversion unit to the floating diffusion region; and a transfer transistor driving circuit configured to control a gate potential of the transfer transistor, wherein the transfer transistor driving circuit controls the gate potential so as to be changed in at least two changing rates during a period of transition from the ON state to the OFF state of the transfer transistor, and the second changing rate out of the two changing rates is higher than the first changing rate.Type: GrantFiled: August 29, 2014Date of Patent: January 24, 2017Assignee: CANON KABUSHIKI KAISHAInventors: Shinichiro Shimizu, Akira Ohtani, Masaru Fujimura
-
Publication number: 20150070554Abstract: A solid-state imaging apparatus includes: a photoelectric conversion unit configured to convert light into an electric charge; a floating diffusion region configured to convert the electric charge into a voltage; a transfer transistor configured to transfer the electric charge from the photoelectric conversion unit to the floating diffusion region; and a transfer transistor driving circuit configured to control a gate potential of the transfer transistor, wherein the transfer transistor driving circuit controls the gate potential so as to be changed in at least two changing rates during a period of transition from the ON state to the OFF state of the transfer transistor, and the second changing rate out of the two changing rates is higher than the first changing rate.Type: ApplicationFiled: August 29, 2014Publication date: March 12, 2015Inventors: Shinichiro Shimizu, Akira Ohtani, Masaru Fujimura
-
Patent number: 8878261Abstract: A semiconductor device comprising a MOS transistor provided in a semiconductor region, wherein a source region and a drain region of the MOS transistor have a first conductivity type, the source region includes a first region including an upper portion of a boundary portion between the source region and a channel region of the MOS transistor, and a second region including an lower portion of the boundary portion, and the first region contains an impurity having a second conductivity type different from the first conductivity type, in an amount larger than that in the second region.Type: GrantFiled: May 8, 2013Date of Patent: November 4, 2014Assignee: Canon Kabushiki KaishaInventor: Akira Ohtani
-
Publication number: 20130321660Abstract: A semiconductor device comprising a MOS transistor provided in a semiconductor region, wherein a source region and a drain region of the MOS transistor have a first conductivity type, the source region includes a first region including an upper portion of a boundary portion between the source region and a channel region of the MOS transistor, and a second region including an lower portion of the boundary portion, and the first region contains an impurity having a second conductivity type different from the first conductivity type, in an amount larger than that in the second region.Type: ApplicationFiled: May 8, 2013Publication date: December 5, 2013Applicant: CANON KABUSHIKI KAISHAInventor: Akira Ohtani
-
Patent number: 8501520Abstract: A manufacturing method for a solid-state image sensor, the method comprises the steps of: forming a charge storage region in a photoelectric converting unit by implanting a semiconductor substrate with ions of an impurity of a first conductivity type, using a first mask; heating the semiconductor substrate at a temperature of no less than 800° C. and no more than 1200° C. through RTA (Rapid Thermal Annealing); forming a surface region of the charge storage region by implanting the semiconductor substrate with ions of an impurity of a second conductivity type, using a second a mask; heating the semiconductor substrate at a temperature of no less than 800° C. and no more than 1200° C. through RTA (Rapid Thermal Annealing); and forming an antireflection film that covers the photoelectric converting unit at a temperature of less than 800° C., after the step of forming the surface region, in this order.Type: GrantFiled: February 1, 2010Date of Patent: August 6, 2013Assignee: Canon Kabushiki KaishaInventors: Katsunori Hirota, Akira Ohtani, Kazuaki Tashiro, Yusuke Onuki, Takanori Watanabe, Takeshi Ichikawa
-
Patent number: 8482646Abstract: An image sensing device comprises a pixel array, and a peripheral circuit, a column selecting circuit, and a readout, wherein each pixel includes a photodiode, a floating diffusion, a transfer PMOS transistor to the floating diffusion, an amplifier PMOS transistor, and a reset PMOS transistor, the amplifier PMOS transistor has a gate which is formed by an n-type conductive pattern, and is isolated by a first element isolation region and an n-type impurity region which covers at least a lower portion of the first element isolation region, and each PMOS transistor included in the column selecting circuit has a gate which is formed by a p-type conductive pattern and is isolated by a second element isolation region, and an n-type impurity concentration in a region adjacent to a lower portion of the second element isolation region is lower than that in the n-type impurity region.Type: GrantFiled: January 20, 2010Date of Patent: July 9, 2013Assignee: Canon Kabushiki KaishaInventors: Takanori Watanabe, Mineo Shimotsusa, Takeshi Ichikawa, Hajime Ikeda, Yasuhiro Sekine, Akira Ohtani, Takeshi Kojima
-
Patent number: 8053272Abstract: A method of fabricating a semiconductor device, comprises steps of forming a common contact hole for a first conductivity-type region and a second conductivity-type region, implanting an impurity in at least one of the first conductivity-type region and the second conductivity-type region, and forming a shared contact plug by filling an electrical conducting material in the contact hole, wherein in the implanting step, an impurity is implanted in at least one of the first conductivity-type region and the second conductivity-type region such that the first conductivity-type region and the shared contact plug are brought into ohmic contact with each other, and the second conductivity-type region and the shared contact plug are brought into ohmic contact with each other.Type: GrantFiled: January 25, 2010Date of Patent: November 8, 2011Assignee: Canon Kabushiki KaishaInventors: Akira Ohtani, Takanori Watanabe, Takeshi Ichikawa
-
Publication number: 20110242388Abstract: An image sensing device comprises a pixel array, and a peripheral circuit, a column selecting circuit, and a readout, wherein each pixel includes a photodiode, a floating diffusion, a transfer PMOS transistor to the floating diffusion, an amplifier PMOS transistor, and a reset PMOS transistor, the amplifier PMOS transistor has a gate which is formed by an n-type conductive pattern, and is isolated by a first element isolation region and an n-type impurity region which covers at least a lower portion of the first element isolation region, and each PMOS transistor included in the column selecting circuit has a gate which is formed by a p-type conductive pattern and is isolated by a second element isolation region, and an n-type impurity concentration in a region adjacent to a lower portion of the second element isolation region is lower than that in the n-type impurity region.Type: ApplicationFiled: January 20, 2010Publication date: October 6, 2011Applicant: CANON KABUSHIKI KAISHAInventors: Takanori Watanabe, Mineo Shimotsusa, Takeshi Ichikawa, Hajime Ikeda, Yasuhiro Sekine, Akira Ohtani, Takeshi Kojima
-
Publication number: 20100203667Abstract: A manufacturing method for a solid-state image sensor, the method comprises the steps of: forming a charge storage region in a photoelectric converting unit by implanting a semiconductor substrate with ions of an impurity of a first conductivity type, using a first mask; heating the semiconductor substrate at a temperature of no less than 800° C. and no more than 1200° C. through RTA (Rapid Thermal Annealing); forming a surface region of the charge storage region by implanting the semiconductor substrate with ions of an impurity of a second conductivity type, using a second a mask; heating the semiconductor substrate at a temperature of no less than 800° C. and no more than 1200° C. through RTA (Rapid Thermal Annealing); and forming an antireflection film that covers the photoelectric converting unit at a temperature of less than 800° C., after the step of forming the surface region, in this order.Type: ApplicationFiled: February 1, 2010Publication date: August 12, 2010Applicant: CANON KABUSHIKI KAISHAInventors: Katsunori Hirota, Akira Ohtani, Kazuaki Tashiro, Yusuke Onuki, Takanori Watanabe, Takeshi Ichikawa
-
Publication number: 20100203670Abstract: A method of fabricating a semiconductor device, comprises steps of forming a common contact hole for a first conductivity-type region and a second conductivity-type region, implanting an impurity in at least one of the first conductivity-type region and the second conductivity-type region, and forming a shared contact plug by filling an electrical conducting material in the contact hole, wherein in the implanting step, an impurity is implanted in at least one of the first conductivity-type region and the second conductivity-type region such that the first conductivity-type region and the shared contact plug are brought into ohmic contact with each other, and the second conductivity-type region and the shared contact plug are brought into ohmic contact with each other.Type: ApplicationFiled: January 25, 2010Publication date: August 12, 2010Applicant: CANON KABUSHIKI KAISHAInventors: Akira Ohtani, Takanori Watanabe, Takeshi Ichikawa
-
Patent number: 7537711Abstract: The invention provides a fuel cell which comprises a solid polymer electrolyte sandwiched between a cathode to which an oxidizing agent gas is supplied and an anode to which a reducing agent gas is supplied, wherein at least one of the electrodes has an electroconductive organic polymer which has an oxidation-reduction function as an electrode catalyst. The invention further provides a fuel cell in which the electrode catalyst comprises a mixture of an electroconductive organic polymer and an inorganic oxidation-reduction catalyst, and has a higher output power.Type: GrantFiled: August 23, 2007Date of Patent: May 26, 2009Assignee: Nitto Denko CorporationInventors: Masao Abe, Akira Ohtani, Kuniaki Ishibashi