Patents by Inventor Akira Oizumi
Akira Oizumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11964639Abstract: A traveling vehicle includes a mechanical brake link mechanism to transmit operation of a brake pedal to a brake device housed in a case and to control brakes of right and left rear wheels. The brake link mechanism includes a pair of brake rods extending in a front-back direction at sides of the case. A guard assembly includes a pair of guards extending in the front-back direction below the pair of brake rods. The pair of brake rods overlaps the pair of guards in a vertical direction. In a side view of the traveling vehicle, the pair of brake rods includes a higher portion positioned above a lower surface of the case to be distanced by a predetermined interval or more and positioned above the lower surface of the case, and a lower portion positioned below the higher portion. The pair of guards overlaps at least all of the lower portions in the vertical direction.Type: GrantFiled: June 24, 2020Date of Patent: April 23, 2024Assignee: KUBOTA CORPORATIONInventors: Takateru Nakagawa, Akira Hiwatashi, Satoshi Oizumi
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Patent number: 10989588Abstract: A sensor device includes: a holder having an insertion hole; a probe having a proximal end to be inserted in the insertion hole and having a portion to be inserted in the insertion hole, a diameter of the portion of the probe to be inserted in the insertion hole being smaller than a hole diameter of the insertion hole; piezoelectric elements housed in the holder, configured to be brought into contact with the proximal end of the probe directly or indirectly, a vibration of the probe acting on the piezoelectric elements; an O-ring (prevention member) disposed in the insertion hole and holding the probe to prevent the probe from contacting the holder, the probe being configured such that a tip of the probe is pushed against a measurement object to detect a vibration of the measurement object.Type: GrantFiled: December 26, 2019Date of Patent: April 27, 2021Assignee: TLV CO., LTD.Inventors: Mamoru Nagase, Akira Oizumi, Hajime Kosaka
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Publication number: 20200149953Abstract: A sensor device includes: a holder having an insertion hole; a probe having a proximal end to be inserted in the insertion hole and having a portion to be inserted in the insertion hole, a diameter of the portion of the probe to be inserted in the insertion hole being smaller than a hole diameter of the insertion hole; piezoelectric elements housed in the holder, configured to be brought into contact with the proximal end of the probe directly or indirectly, a vibration of the probe acting on the piezoelectric elements; an O-ring (prevention member) disposed in the insertion hole and holding the probe to prevent the probe from contacting the holder, the probe being configured such that a tip of the probe is pushed against a measurement object to detect a vibration of the measurement object.Type: ApplicationFiled: December 26, 2019Publication date: May 14, 2020Applicant: TLV CO., LTD.Inventors: Mamoru NAGASE, Akira OIZUMI, Hajime KOSAKA
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Patent number: 10331204Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: GrantFiled: March 8, 2018Date of Patent: June 25, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
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Patent number: 10317981Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.Type: GrantFiled: December 6, 2016Date of Patent: June 11, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Patent number: 10110060Abstract: The disclosed invention is intended to prevent malfunction of an internal circuit because of unwanted power supply switching caused by a noise during operation of a semiconductor device powered by a backup power supply, while eliminating wasteful consumption of the backup power supply. A first switching transition time after coupling the main power supply terminal to the internal power supply node until decoupling the backup power supply terminal from the internal power supply node is made longer than a second switching transition time after coupling the backup power supply terminal to the internal power supply node until decoupling the main power supply terminal from the internal power supply node.Type: GrantFiled: September 12, 2017Date of Patent: October 23, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tomoki Yasukawa, Akira Oizumi, Toyohiko Yoshida, Yoshinori Tokioka
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Publication number: 20180196500Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: ApplicationFiled: March 8, 2018Publication date: July 12, 2018Inventors: Yoshinori TOKIOKA, Soichi KOBAYASHI, Akira OIZUMI
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Patent number: 9946332Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: GrantFiled: February 22, 2017Date of Patent: April 17, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
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Publication number: 20180006491Abstract: The disclosed invention is intended to prevent malfunction of an internal circuit because of unwanted power supply switching caused by a noise during operation of a semiconductor device powered by a backup power supply, while eliminating wasteful consumption of the backup power supply. A first switching transition time after coupling the main power supply terminal to the internal power supply node until decoupling the backup power supply terminal from the internal power supply node is made longer than a second switching transition time after coupling the backup power supply terminal to the internal power supply node until decoupling the main power supply terminal from the internal power supply node.Type: ApplicationFiled: September 12, 2017Publication date: January 4, 2018Inventors: Tomoki YASUKAWA, Akira OIZUMI, Toyohiko YOSHIDA, Yoshinori TOKIOKA
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Patent number: 9787135Abstract: The disclosed invention is intended to prevent malfunction of an internal circuit because of unwanted power supply switching caused by a noise during operation of a semiconductor device powered by a backup power supply, while eliminating wasteful consumption of the backup power supply. A first switching transition time after coupling the main power supply terminal to the internal power supply node until decoupling the backup power supply terminal from the internal power supply node is made longer than a second switching transition time after coupling the backup power supply terminal to the internal power supply node until decoupling the main power supply terminal from the internal power supply node.Type: GrantFiled: September 2, 2015Date of Patent: October 10, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tomoki Yasukawa, Akira Oizumi, Toyohiko Yoshida, Yoshinori Tokioka
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Publication number: 20170160792Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: ApplicationFiled: February 22, 2017Publication date: June 8, 2017Inventors: Yoshinori TOKIOKA, Soichi KOBAYASHI, Akira OIZUMI
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Patent number: 9612644Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: GrantFiled: September 3, 2015Date of Patent: April 4, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
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Publication number: 20170083080Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Patent number: 9529402Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.Type: GrantFiled: September 2, 2010Date of Patent: December 27, 2016Assignee: Renesas Electronics CorporationInventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Publication number: 20160065001Abstract: The disclosed invention is intended to prevent malfunction of an internal circuit because of unwanted power supply switching caused by a noise during operation of a semiconductor device powered by a backup power supply, while eliminating wasteful consumption of the backup power supply. A first switching transition time after coupling the main power supply terminal to the internal power supply node until decoupling the backup power supply terminal from the internal power supply node is made longer than a second switching transition time after coupling the backup power supply terminal to the internal power supply node until decoupling the main power supply terminal from the internal power supply node.Type: ApplicationFiled: September 2, 2015Publication date: March 3, 2016Inventors: Tomoki YASUKAWA, Akira OIZUMI, Toyohiko YOSHIDA, Yoshinori TOKIOKA
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Publication number: 20150378426Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: ApplicationFiled: September 3, 2015Publication date: December 31, 2015Inventors: Yoshinori TOKIOKA, Soichi KOBAYASHI, Akira OIZUMI
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Patent number: 9166601Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: GrantFiled: September 25, 2013Date of Patent: October 20, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
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Patent number: 9130574Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: GrantFiled: September 25, 2013Date of Patent: September 8, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
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Publication number: 20150155854Abstract: There is a need to provide a technology that shortens a time period from a point to start an external power supply for a microcontroller to a point to start operating a logic circuit. A stable voltage supply circuit of a semiconductor circuit accepts an external power supply VCC and supplies a VDD line with one of a power supply voltage to cause a stable output voltage and a power supply voltage to cause an unstable output voltage and fast start. At startup, the semiconductor circuit accepts an external power supply. The semiconductor circuit raises a power supply voltage to cause a stable output voltage and supplies a logic portion initialization circuit with an unstable power supply voltage to fast start, and initializes a VDD operation circuit. When the output voltage is stabilized, the semiconductor circuit changes a power supply voltage supplied to the VDD line and starts operating the VDD operation circuit.Type: ApplicationFiled: November 19, 2014Publication date: June 4, 2015Inventors: Keiichi HAYASAKA, Toyohiko YOSHIDA, Akira OIZUMI, Yoshinori TOKIOKA
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Patent number: D1001655Type: GrantFiled: September 30, 2021Date of Patent: October 17, 2023Assignee: TLV CO., LTD.Inventors: Mamoru Nagase, Akira Oizumi, Masashi Matsumoto, Eiji Takenaka, Hiroshi Shiromoto